Bug 25332 - Error: selected processor does not support `stclrb w2,[x1]' for cortex-a53
Summary: Error: selected processor does not support `stclrb w2,[x1]' for cortex-a53
Alias: None
Product: binutils
Classification: Unclassified
Component: gas (show other bugs)
Version: 2.32
: P2 normal
Target Milestone: ---
Assignee: Not yet assigned to anyone
Depends on:
Reported: 2020-01-01 18:12 UTC by Pete Moore
Modified: 2020-01-01 21:29 UTC (History)
1 user (show)

See Also:
Last reconfirmed:


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Description Pete Moore 2020-01-01 18:12:31 UTC
GNU gas 2.32 considers that the A64 instruction stclrb instruction is not supported on cortex-a53, however this differs from my understanding of the ARM documentation.

gas version:

$ /usr/local/bin/aarch64-unknown-linux-gnu-as --version
GNU assembler (crosstool-NG 1.24.0) 2.32
Copyright (C) 2019 Free Software Foundation, Inc.
This program is free software; you may redistribute it under the terms of
the GNU General Public License version 3 or later.
This program has absolutely no warranty.
This assembler was configured for a target of `aarch64-unknown-linux-gnu'.

Test code:

$ cat stclrb.s 
.arch armv8-a
.cpu cortex-a53
.global _start
  stclrb w2, [x1]

Assembler output:

$ /usr/local/bin/aarch64-unknown-linux-gnu-as -mcpu=cortex-a53 -mverbose-error -g -o stclrb stclrb.s 
stclrb.s: Assembler messages:
stclrb.s:6: Error: selected processor does not support `stclrb w2,[x1]'

The Arm Cortex-A53 MPCore Processor Technical Reference Manual Revision r0p4[1] says:

> 1.2.1. Arm architecture
> The Cortex-A53 processor implements the Armv8-A architecture. This includes:
>   * Support for both AArch32 and AArch64 Execution states.
>   * Support for all Exception levels, EL0, EL1, EL2, and EL3, in each execution state.
>   * The A32 instruction set, previously called the Arm instruction set.
>   * The T32 instruction set, previously called the Thumb instruction set.
>   * The A64 instruction set.

The A64 instruction set of the Armv8-A architecture is described in the "Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile"[2], and in the most recent version of this document (version ea[3]) at the time of writing, the STCLRB instruction is defined in section "C6.2 Alphabetical list of A64 base instructions" under subsection C6.2.249 with heading "STCLRB, STCLRLB".

I therefore am led to believe that STCLRB indeed is part of the base A64 instruction set of the ARMv8-A architecture (not an optional architecture extension), supported by the ARM Cortex A53 MP Core Processor, and therefore that this example test program should compile without reporting an error.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500j/BABHJJBC.html
[2] https://developer.arm.com/docs/ddi0487/ea/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
[3] https://static.docs.arm.com/ddi0487/ea/DDI0487E_a_armv8_arm.pdf?_ga=2.16163382.1622503159.1577875323-1539468621.1577875323
Comment 1 Pete Moore 2020-01-01 21:00:26 UTC
Digging a little deeper, it looks like this instruction is part of "ARMv8.1-LSE, Armv8.1 Large System Extensions".

From the Arm Cortex-A53 MPCore Processor Technical Reference Manual, it isn't clear to me if the Cortex A53 supports ARMv8.1, but https://en.wikipedia.org/wiki/Comparison_of_ARMv8-A_cores suggests it only supports ARMv8.0-A, so maybe this is an invalid bug.

Apologies if this is the case, although I'd be grateful if someone can confirm for sure. The TRM states "The Cortex-A53 processor implements the Armv8-A architecture" but I don't see a reference to the version of Armv8-A that it supports in that document, but if the wiki page is correct, that would explain why gas gives this error message...

Many thanks!
Comment 2 Tamar Christina 2020-01-01 21:21:22 UTC
We don't refer to Armv8-A baseline as Armv8.0-A, so when you see Armv8-A it usually means baseline.

Cortex-A53 is one of the first cores to implement Armv8 and so doesn't support LSE.

You can see this on the table at https://developer.arm.com/ip-products/processors/cortex-a/cortex-a53 if you scroll down to `Cortex-A comparison table (Armv8-A)`.

You'll see that the cores that support another architecture extension explicitly lists them.

So yes in this case the table is accurate :)
Comment 3 Pete Moore 2020-01-01 21:29:01 UTC
Many thanks Tamar!

I've also just now seen in the description of MIDR_EL1 in the TRM, that the "Variant" is 0, which I guess also suggests v0(?)

Thanks for following up so quickly, and again sorry for the noise!

Best wishes, Pete.