Bug 12329 - avr-objdump -d: wrong op-code
Summary: avr-objdump -d: wrong op-code
Status: RESOLVED FIXED
Alias: None
Product: binutils
Classification: Unclassified
Component: binutils (show other bugs)
Version: 2.20
: P2 normal
Target Milestone: ---
Assignee: unassigned
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2010-12-16 17:30 UTC by Jesús Arias
Modified: 2011-07-01 16:14 UTC (History)
1 user (show)

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Description Jesús Arias 2010-12-16 17:30:06 UTC
The instruction:

    LPM  Rx,Z

is dissasembled as:

    LPM  Rx,Z+

I found this while inspecting code for an ATtiny2313:

 714:	24 91       	lpm	r18, Z+

The op-code 0x9124  should be "LPM R18,Z". Wrong post-increment addressing.
Comment 1 cvs-commit@gcc.gnu.org 2011-07-01 16:11:32 UTC
CVSROOT:	/cvs/src
Module name:	src
Changes by:	nickc@sourceware.org	2011-07-01 16:11:27

Modified files:
	opcodes        : ChangeLog arm-dis.c avr-dis.c 
	include/opcode : ChangeLog avr.h 

Log message:
	PR binutils/12329
	* avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
	insns using post-increment addressing.
	
	* avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.

Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.1740&r2=1.1741
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/arm-dis.c.diff?cvsroot=src&r1=1.146&r2=1.147
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/avr-dis.c.diff?cvsroot=src&r1=1.23&r2=1.24
http://sourceware.org/cgi-bin/cvsweb.cgi/src/include/opcode/ChangeLog.diff?cvsroot=src&r1=1.441&r2=1.442
http://sourceware.org/cgi-bin/cvsweb.cgi/src/include/opcode/avr.h.diff?cvsroot=src&r1=1.16&r2=1.17
Comment 2 Nick Clifton 2011-07-01 16:14:00 UTC
Hi Jesús,

  Thanks for reporting this problem.  I have checked in a patch to fix the disassembly of the LPM instruction, and incidentally the ELPM and SPM instructions which had the same problem.

Cheers
  Nick