Bug 11891 - linker changes target register in tlsgd load
Summary: linker changes target register in tlsgd load
Status: RESOLVED FIXED
Alias: None
Product: binutils
Classification: Unclassified
Component: ld (show other bugs)
Version: 2.20
: P2 normal
Target Milestone: ---
Assignee: Richard Henderson
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2010-08-06 18:37 UTC by Uros Bizjak
Modified: 2010-08-10 00:02 UTC (History)
1 user (show)

See Also:
Host: alphaev68-pc-linux-gnu
Target: alphaev68-pc-linux-gnu
Build: alphaev68-pc-linux-gnu
Last reconfirmed:


Attachments
Asm dump (426 bytes, text/plain)
2010-08-06 18:39 UTC, Uros Bizjak
Details

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Description Uros Bizjak 2010-08-06 18:37:50 UTC
Soon to be attached asm dump is produced by compiling:

__thread a;

int
main ()
{
  a = 0;
}

with -O2 -fpic on native-TLS architecture.

To show the problem, a tlsgd load was changed from:

	lda $16,a($29)		!tlsgd!1
to:
	lda $15,a($29)		!tlsgd!1
	mov $15,$16

(this change illustrates real code, produced by compiling the testcase from
gcc.dg/tls/opt-12.c.

The object file is still OK (see insn at 0x10):

0000000000000000 <main>:
   0:	00 00 bb 27 	ldah	gp,0(t12)
   4:	00 00 bd 23 	lda	gp,0(gp)
   8:	f0 ff de 23 	lda	sp,-16(sp)
   c:	1f 04 ff 5f 	fnop	
> 10:	00 00 fd 21 	lda	fp,0(gp)                     <<<<< HERE
  14:	10 04 ef 47 	mov	fp,a0
  18:	00 00 7d a7 	ldq	t12,0(gp)
  1c:	00 00 5e b7 	stq	ra,0(sp)
  20:	00 40 5b 6b 	jsr	ra,(t12),24 <main+0x24>
  24:	00 00 ba 27 	ldah	gp,0(ra)
  28:	00 00 5e a7 	ldq	ra,0(sp)
  2c:	00 00 e0 b3 	stl	zero,0(v0)
  30:	00 00 bd 23 	lda	gp,0(gp)
  34:	10 00 de 23 	lda	sp,16(sp)
  38:	01 80 fa 6b 	ret
  3c:	00 00 fe 2f 	unop	

However, final link changes target reg in the marked insn from fp to a0:

0000000120000640 <main>:
   120000640:	02 00 bb 27 	ldah	gp,2(t12)
   120000644:	d0 99 bd 23 	lda	gp,-26160(gp)
   120000648:	f0 ff de 23 	lda	sp,-16(sp)
   12000064c:	1f 04 ff 5f 	fnop	
>  120000650:	10 00 1f 22 	lda	a0,16
   120000654:	10 04 ef 47 	mov	fp,a0
   120000658:	00 00 fe 2f 	unop	
   12000065c:	00 00 5e b7 	stq	ra,0(sp)
   120000660:	9e 00 00 00 	rduniq
   120000664:	00 04 00 42 	addq	a0,v0,v0
   120000668:	00 00 5e a7 	ldq	ra,0(sp)
   12000066c:	00 00 e0 b3 	stl	zero,0(v0)
   120000670:	00 00 fe 2f 	unop	
   120000674:	10 00 de 23 	lda	sp,16(sp)
   120000678:	01 80 fa 6b 	ret
   12000067c:	00 00 fe 2f 	unop	

There is no need for this "fixup".
Comment 1 Uros Bizjak 2010-08-06 18:39:02 UTC
Created attachment 4918 [details]
Asm dump
Comment 2 Sourceware Commits 2010-08-09 23:59:05 UTC
Subject: Bug 11891

CVSROOT:	/cvs/src
Module name:	src
Changes by:	rth@sourceware.org	2010-08-09 23:58:52

Modified files:
	bfd            : ChangeLog elf64-alpha.c 

Log message:
	PR ld/11891
	* elf64-alpha.c (elf64_alpha_relax_tls_get_addr): Disallow relaxing
	to tlshi/lo until pos0 and pos1 are adjacent.  Use the destination
	register from the tldgd insn.

Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/bfd/ChangeLog.diff?cvsroot=src&r1=1.5100&r2=1.5101
http://sourceware.org/cgi-bin/cvsweb.cgi/src/bfd/elf64-alpha.c.diff?cvsroot=src&r1=1.168&r2=1.169

Comment 3 Richard Henderson 2010-08-10 00:02:39 UTC
Fixed.