| Summary: | generates "illegal" opcodes in unified mode instead of error | ||
|---|---|---|---|
| Product: | binutils | Reporter: | 42Bastian <bastian.schick> |
| Component: | gas | Assignee: | unassigned |
| Status: | WAITING --- | ||
| Severity: | normal | CC: | bug-binutils |
| Priority: | P2 | ||
| Version: | 2.19 | ||
| Target Milestone: | --- | ||
| Host: | i686-pc-cygwin | Target: | arm-none-eabi |
| Build: | i686-pc-cygwin | Last reconfirmed: | |
| Attachments: | Catch use of illegal copy instruction | ||
Re-read ARM ARM: mov rn,rm with rn and rm low-register is illegal. Changed "Severity" to normal, as I judge this a bug. Hi Bastian, This is not a bug. The assembler is quite reasonably translating the requested operation (move low register to low register whilst setting the status bits) into a machine instruction that will perform the operation. The fact that it needs to use an ADDS opcode instead of a MOVS opcode is a technical issue, not a cause for the assembler to generate an error. Cheers Nick (In reply to comment #2) Hi Nick > This is not a bug. The assembler is quite reasonably translating the > requested operation (move low register to low register whilst setting the status > bits) into a machine instruction that will perform the operation. The fact that > it needs to use an ADDS opcode instead of a MOVS opcode is a technical issue, > not a cause for the assembler to generate an error. Maybe I was not clear enough. The second opcode is correct, as you describe. But the "mov r1,r0" is incorrect for ARMv4T,ARMv5T machines. Check ARM ARM A7.1.44 : " If H1==0 and H2==0 in the encoding, the instruction specifies a non-flag-setting copy move from one low register to another low register. This instruction cannot be written using the MOV syntax, because MOV <Rd>, <Rm> generates a flag-setting copy. However, you can write it using the CPY mnemonic, see CPY on page A7-41. Note Prior to ARMv6, specifying a low register for <Rd> and <Rm> (H1 == 0 and H2 == 0), the result is UNPREDICTABLE." Since the CPU selected (XScale) is ARMv5TE, I still thing it is a bug. Created attachment 3895 [details]
Catch use of illegal copy instruction
Hi Bastian, Ah - sorry about that. Now that I understand the problem, please could you examine the uploaded patch which I think will address the issue for you. Cheers Nick |
GAS generates "illegal" opcodes instead of showing a warning or error if wrong assembly code is entered in unified mode. Worse: E.g. XScale excecutes the illegal opcodes. Example: arm-none-eabi-as -mcpu=xscale .syntax unified .code 16 mov r1,r0 movs r1,r0 Result: 0000000 <.text>: 0: 4601 mov r1, r0 2: 1c01 adds r1, r0, #0 0: - Illegal opcode for XScale, move w/o setting flags. Note: According ARM ARM the opcode is valid, but the old syntax does not allow to choose two lower registers. IMHO, a warning should be issued if a none-T2 cpu is selected.