Bug 19721

Summary: [libopcodes] [Aarch64] Incorrect aliasing for ORR instruction
Product: binutils Reporter: nholcomb
Component: binutilsAssignee: Not yet assigned to anyone <unassigned>
Severity: normal CC: nickc
Priority: P2    
Version: 2.26   
Target Milestone: ---   
Host: Target:
Build: Last reconfirmed:

Description nholcomb 2016-02-24 21:28:22 UTC
The libopcodes decoder for aarch64 incorrectly aliases ORR instructions with the zero register but non-zero shift values to MOV instructions without signifying the shift.

Below is GDB output with register info after executing one such instruction (0xaa1167e):

(gdb) x/x 0x400588
0x400588 <main+16>:  0xaa1167e
(gdb) x/i $pc
=> 0x400588 <main+16>:  mov   x7, x17
(gdb) info registers
x7             0x83322
x17            0x4109d8
(gdb) stepi
0x000000000040058c in main ()
(gdb) info registers
x7             0x8213b0000000
x17            0x4109d8

The instruction correct interpretation should be the ORR instruction with a left shift of 25 bits.
Comment 1 cvs-commit@gcc.gnu.org 2016-03-18 17:04:57 UTC
The master branch has been updated by Nick Clifton <nickc@sourceware.org>:


commit 8678914fcb40e4c620a33e6b38a14df928fa780a
Author: Nick Clifton <nickc@redhat.com>
Date:   Fri Mar 18 17:02:20 2016 +0000

    Fix the disassembly of the AArch64's OOR instruction as a MOV instruction.
    	PR target/19721
    opcodes	* aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
    	of MOV insn that aliases an ORR insn.
    gas	* testsuite/gas/aarch64/pr19721.s: New test source file.
    	* testsuite/gas/aarch64/pr19721.d: New test driver file.
Comment 2 Nick Clifton 2016-03-18 17:09:50 UTC
I have checked in a patch to fix this.  If you have any more problems like this, please feel free to reopen this PR, or file a new bug report.

Comment 3 cvs-commit@gcc.gnu.org 2018-12-03 17:35:41 UTC
The master branch has been updated by Richard Earnshaw <rearnsha@sourceware.org>:


commit 57b64c4103ffeadd524eb80b4a7d61be8c8ec871
Author: Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
Date:   Mon Dec 3 17:31:44 2018 +0000

    [aarch64] - Only use MOV for disassembly when shifter op is LSL #0
    ARM Architecture Reference Manual for the profile ARMv8-A, Issue C.a,
    states that MOV (register) is an alias of the ORR (shifted register)
    iff shift == '00' && imm6 == '000000' && Rn == '11111'.  However, mov
    is currently preferred for a broader range of orr instructions, which
    is incorrect.
    2018-12-03  Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
    	PR 23193
            PR 19721
            * aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR
    	encoding as MOV if the shift operation is a left shift of zero.
    	PR 23193
    	PR 19721
    	* testsuite/gas/aarch64/pr19721.s: Add new test cases.
    	* testsuite/gas/aarch64/pr19721.d: Correct existing test
    	cases and add new ones.