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(-)glibc/sysdeps/powerpc/fpu/feholdexcpt.c (-2 / +4 lines)
Lines 1-5 Link Here
1
/* Store current floating-point environment and clear exceptions.
1
/* Store current floating-point environment and clear exceptions.
2
   Copyright (C) 1997, 2005 Free Software Foundation, Inc.
2
   Copyright (C) 1997, 2005, 2008 Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
3
   This file is part of the GNU C Library.
4
4
5
   The GNU C Library is free software; you can redistribute it and/or
5
   The GNU C Library is free software; you can redistribute it and/or
Lines 18-23 Link Here
18
   02111-1307 USA.  */
18
   02111-1307 USA.  */
19
19
20
#include <fenv_libc.h>
20
#include <fenv_libc.h>
21
#include <fpu_control.h>
22
#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM)
21
23
22
int
24
int
23
feholdexcept (fenv_t *envp)
25
feholdexcept (fenv_t *envp)
Lines 35-41 Link Here
35
  /* If the old env had any eabled exceptions, then mask SIGFPE in the
37
  /* If the old env had any eabled exceptions, then mask SIGFPE in the
36
     MSR FE0/FE1 bits.  This may allow the FPU to run faster because it
38
     MSR FE0/FE1 bits.  This may allow the FPU to run faster because it
37
     always takes the default action and can not generate SIGFPE. */
39
     always takes the default action and can not generate SIGFPE. */
38
  if ((old.l[1] & 0x000000F8) != 0)
40
  if ((old.l[1] & _FPU_MASK_ALL) != 0)
39
    (void)__fe_mask_env ();
41
    (void)__fe_mask_env ();
40
42
41
  /* Put the new state in effect.  */
43
  /* Put the new state in effect.  */
(-)glibc/sysdeps/powerpc/fpu/fenv_libc.h (-2 / +24 lines)
Lines 21-26 Link Here
21
#define _FENV_LIBC_H	1
21
#define _FENV_LIBC_H	1
22
22
23
#include <fenv.h>
23
#include <fenv.h>
24
#include <ldsodefs.h>
25
#include <sysdep.h>
24
26
25
libm_hidden_proto (__fe_nomask_env)
27
libm_hidden_proto (__fe_nomask_env)
26
28
Lines 34-40 Link Here
34
36
35
/* Equivalent to fesetenv, but takes a fenv_t instead of a pointer.  */
37
/* Equivalent to fesetenv, but takes a fenv_t instead of a pointer.  */
36
#define fesetenv_register(env) \
38
#define fesetenv_register(env) \
37
        ({ double d = (env); asm volatile ("mtfsf 0xff,%0" : : "f" (d)); })
39
	do { \
40
	  double d = (env); \
41
	  if(GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
42
	    asm volatile ("mtfsf 0xff,%0,1,0" : : "f" (d)); \
43
	  else \
44
	    asm volatile ("mtfsf 0xff,%0" : : "f" (d)); \
45
	} while(0)
38
46
39
/* This very handy macro:
47
/* This very handy macro:
40
   - Sets the rounding mode to 'round to nearest';
48
   - Sets the rounding mode to 'round to nearest';
Lines 42-48 Link Here
42
   - Prevents exceptions from being raised for inexact results.
50
   - Prevents exceptions from being raised for inexact results.
43
   These things happen to be exactly what you need for typical elementary
51
   These things happen to be exactly what you need for typical elementary
44
   functions.  */
52
   functions.  */
45
#define relax_fenv_state() asm ("mtfsfi 7,0")
53
#define relax_fenv_state() \
54
	do { \
55
	   if(GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
56
	       asm ("mtfsfi 7,0,1"); \
57
	   asm ("mtfsfi 7,0"); \
58
	} while(0)
46
59
47
/* Set/clear a particular FPSCR bit (for instance,
60
/* Set/clear a particular FPSCR bit (for instance,
48
   reset_fpscr_bit(FPSCR_VE);
61
   reset_fpscr_bit(FPSCR_VE);
Lines 122-131 Link Here
122
  FPSCR_UE,        /* underflow exception enable */
135
  FPSCR_UE,        /* underflow exception enable */
123
  FPSCR_ZE,        /* zero divide exception enable */
136
  FPSCR_ZE,        /* zero divide exception enable */
124
  FPSCR_XE,        /* inexact exception enable */
137
  FPSCR_XE,        /* inexact exception enable */
138
#if defined _ARCH_PWR6
139
  FPSCR_29,        /* Reserved in ISA 2.05  */
140
#else
125
  FPSCR_NI         /* non-IEEE mode (typically, no denormalised numbers) */
141
  FPSCR_NI         /* non-IEEE mode (typically, no denormalised numbers) */
142
#endif /* _ARCH_PWR6 */
126
  /* the remaining two least-significant bits keep the rounding mode */
143
  /* the remaining two least-significant bits keep the rounding mode */
127
};
144
};
128
145
146
#if defined _ARCH_PWR6
147
  /* Not supported in ISA 2.05.  Provided for source compat only.  */
148
# define FPSCR_NI 29
149
#endif /* _ARCH_PWR6 */
150
129
/* This operation (i) sets the appropriate FPSCR bits for its
151
/* This operation (i) sets the appropriate FPSCR bits for its
130
   parameter, (ii) converts SNaN to the corresponding NaN, and (iii)
152
   parameter, (ii) converts SNaN to the corresponding NaN, and (iii)
131
   otherwise passes its parameter through unchanged (in particular, -0
153
   otherwise passes its parameter through unchanged (in particular, -0
(-)glibc/sysdeps/powerpc/fpu/fesetenv.c (-8 / +12 lines)
Lines 1-5 Link Here
1
/* Install given floating-point environment.
1
/* Install given floating-point environment.
2
   Copyright (C) 1997,99,2000,01,02,07 Free Software Foundation, Inc.
2
   Copyright (C) 1997, 1999, 2000, 2001, 2007, 2008
3
   Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
4
   This file is part of the GNU C Library.
4
5
5
   The GNU C Library is free software; you can redistribute it and/or
6
   The GNU C Library is free software; you can redistribute it and/or
Lines 18-25 Link Here
18
   02111-1307 USA.  */
19
   02111-1307 USA.  */
19
20
20
#include <fenv_libc.h>
21
#include <fenv_libc.h>
22
#include <fpu_control.h>
21
#include <bp-sym.h>
23
#include <bp-sym.h>
22
24
25
#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM)
26
23
int
27
int
24
__fesetenv (const fenv_t *envp)
28
__fesetenv (const fenv_t *envp)
25
{
29
{
Lines 29-46 Link Here
29
  new.fenv = *envp;
33
  new.fenv = *envp;
30
  old.fenv = fegetenv_register ();
34
  old.fenv = fegetenv_register ();
31
  
35
  
32
  /* If the old env has no eabled exceptions and the new env has any enabled
36
  /* If the old env has no enabled exceptions and the new env has any enabled
33
     exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits.  This will put
37
     exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits.  This will put the
34
     the hardware into "precise mode" and may cause the FPU to run slower on
38
     hardware into "precise mode" and may cause the FPU to run slower on some
35
     some hardware.  */
39
     hardware.  */
36
  if ((old.l[1] & 0x000000F8) == 0 && (new.l[1] & 0x000000F8) != 0)
40
  if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0)
37
    (void)__fe_nomask_env ();
41
    (void)__fe_nomask_env ();
38
  
42
  
39
  /* If the old env had any eabled exceptions and the new env has no enabled
43
  /* If the old env had any enabled exceptions and the new env has no enabled
40
     exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
44
     exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
41
     FPU to run faster because it always takes the default action and can not 
45
     FPU to run faster because it always takes the default action and can not 
42
     generate SIGFPE. */
46
     generate SIGFPE. */
43
  if ((old.l[1] & 0x000000F8) != 0 && (new.l[1] & 0x000000F8) == 0)
47
  if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0)
44
    (void)__fe_mask_env ();
48
    (void)__fe_mask_env ();
45
    
49
    
46
  fesetenv_register (*envp);
50
  fesetenv_register (*envp);
(-)glibc/sysdeps/powerpc/fpu/feupdateenv.c (-3 / +7 lines)
Lines 1-5 Link Here
1
/* Install given floating-point environment and raise exceptions.
1
/* Install given floating-point environment and raise exceptions.
2
   Copyright (C) 1997,99,2000,01,07 Free Software Foundation, Inc.
2
   Copyright (C) 1997, 1999, 2000, 2001, 2007, 2008
3
   Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
4
   This file is part of the GNU C Library.
4
   Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997.
5
   Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997.
5
6
Lines 19-26 Link Here
19
   02111-1307 USA.  */
20
   02111-1307 USA.  */
20
21
21
#include <fenv_libc.h>
22
#include <fenv_libc.h>
23
#include <fpu_control.h>
22
#include <bp-sym.h>
24
#include <bp-sym.h>
23
25
26
#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM)
27
24
int
28
int
25
__feupdateenv (const fenv_t *envp)
29
__feupdateenv (const fenv_t *envp)
26
{
30
{
Lines 39-52 Link Here
39
     exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits.  This will put
43
     exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits.  This will put
40
     the hardware into "precise mode" and may cause the FPU to run slower on
44
     the hardware into "precise mode" and may cause the FPU to run slower on
41
     some hardware.  */
45
     some hardware.  */
42
  if ((old.l[1] & 0x000000F8) == 0 && (new.l[1] & 0x000000F8) != 0)
46
  if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0)
43
    (void)__fe_nomask_env ();
47
    (void)__fe_nomask_env ();
44
  
48
  
45
  /* If the old env had any eabled exceptions and the new env has no enabled
49
  /* If the old env had any eabled exceptions and the new env has no enabled
46
     exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
50
     exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
47
     FPU to run faster because it always takes the default action and can not 
51
     FPU to run faster because it always takes the default action and can not 
48
     generate SIGFPE. */
52
     generate SIGFPE. */
49
  if ((old.l[1] & 0x000000F8) != 0 && (new.l[1] & 0x000000F8) == 0)
53
  if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0)
50
    (void)__fe_mask_env ();
54
    (void)__fe_mask_env ();
51
55
52
  /* Atomically enable and raise (if appropriate) exceptions set in `new'. */
56
  /* Atomically enable and raise (if appropriate) exceptions set in `new'. */
(-)glibc/sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/setcontext.S (+2 lines)
Line 0 Link Here
1
#define _ARCH_PWR6
2
#include_next <setcontext.S>
(-)glibc/sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/swapcontext.S (+2 lines)
Line 0 Link Here
1
#define _ARCH_PWR6
2
#include_next <swapcontext.S>
(-)glibc/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S (-14 / +28 lines)
Lines 1-5 Link Here
1
/* Jump to a new context powerpc32 common.
1
/* Jump to a new context powerpc32 common.
2
   Copyright (C) 2005, 2006 Free Software Foundation, Inc.
2
   Copyright (C) 2005, 2006, 2008 Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
3
   This file is part of the GNU C Library.
4
4
5
   The GNU C Library is free software; you can redistribute it and/or
5
   The GNU C Library is free software; you can redistribute it and/or
Lines 71-103 Link Here
71
	cmpwi	r3,0
71
	cmpwi	r3,0
72
	bne	3f	/* L(error_exit) */
72
	bne	3f	/* L(error_exit) */
73
73
74
#ifdef __CONTEXT_ENABLE_FPRS
74
#ifdef PIC
75
# ifdef __CONTEXT_ENABLE_VRS
76
#  ifdef PIC
77
	mflr    r8
75
	mflr    r8
78
#   ifdef HAVE_ASM_PPC_REL16
76
# ifdef HAVE_ASM_PPC_REL16
79
	bcl	20,31,1f
77
	bcl	20,31,1f
80
1:	mflr	r7
78
1:	mflr	r7
81
	addis	r7,r7,_GLOBAL_OFFSET_TABLE_-1b@ha
79
	addis	r7,r7,_GLOBAL_OFFSET_TABLE_-1b@ha
82
	addi	r7,r7,_GLOBAL_OFFSET_TABLE_-1b@l
80
	addi	r7,r7,_GLOBAL_OFFSET_TABLE_-1b@l
83
#   else
81
# else
84
	bl      _GLOBAL_OFFSET_TABLE_@local-4
82
	bl      _GLOBAL_OFFSET_TABLE_@local-4
85
	mflr    r7
83
	mflr    r7
86
#   endif
84
# endif
87
#   ifdef SHARED
85
# ifdef SHARED
88
	lwz     r7,_rtld_global_ro@got(r7)
86
	lwz     r7,_rtld_global_ro@got(r7)
89
	mtlr    r8
87
	mtlr    r8
90
	lwz     r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
88
	lwz     r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
91
#   else
89
# else
92
	lwz     r7,_dl_hwcap@got(r7)
90
	lwz     r7,_dl_hwcap@got(r7)
93
	mtlr    r8
91
	mtlr    r8
94
	lwz     r7,0(r7)
92
	lwz     r7,0(r7)
95
#   endif
93
# endif
96
#  else
94
#else
97
	lis	r7,_dl_hwcap@ha
95
	lis	r7,_dl_hwcap@ha
98
	lwz     r7,_dl_hwcap@l(r7)
96
	lwz     r7,_dl_hwcap@l(r7)
99
#  endif
97
#endif
100
	andis.	r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
98
99
#ifdef __CONTEXT_ENABLE_FPRS
100
# ifdef __CONTEXT_ENABLE_VRS
101
	andis.	r6,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
101
	la	r10,(_UC_VREGS)(r31)
102
	la	r10,(_UC_VREGS)(r31)
102
	beq	2f	/* L(has_no_vec) */
103
	beq	2f	/* L(has_no_vec) */
103
104
Lines 199-205 Link Here
199
	/* Restore the floating-point registers */
200
	/* Restore the floating-point registers */
200
	lfd	fp31,_UC_FREGS+(32*8)(r31)
201
	lfd	fp31,_UC_FREGS+(32*8)(r31)
201
	lfd	fp0,_UC_FREGS+(0*8)(r31)
202
	lfd	fp0,_UC_FREGS+(0*8)(r31)
202
	mtfsf	0xff,fp31
203
# if defined _ARCH_PWR6
204
	/* Use the extended four-operand version of the mtfsf insn.  */
205
	mtfsf  0xff,fp0,1,0
206
# else
207
	/* Availability of DFP indicates a 64-bit FPSCR.  */
208
	andi.	r6,r7,PPC_FEATURE_HAS_DFP
209
	bne	7f
210
	/* Use the extended four-operand version of the mtfsf insn.  */
211
	mtfsf	0xff,fp31,1,0
212
	b	8f
213
	/* Continue to operate on the FPSCR as if it were 32-bits.  */
214
7:	mtfsf	0xff,fp31
215
8:
216
# endif /* _ARCH_PWR6 */
203
	lfd	fp1,_UC_FREGS+(1*8)(r31)
217
	lfd	fp1,_UC_FREGS+(1*8)(r31)
204
	lfd	fp2,_UC_FREGS+(2*8)(r31)
218
	lfd	fp2,_UC_FREGS+(2*8)(r31)
205
	lfd	fp3,_UC_FREGS+(3*8)(r31)
219
	lfd	fp3,_UC_FREGS+(3*8)(r31)
(-)glibc/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S (-14 / +28 lines)
Lines 1-5 Link Here
1
/* Save current context and jump to a new context.
1
/* Save current context and jump to a new context.
2
   Copyright (C) 2005, 2006 Free Software Foundation, Inc.
2
   Copyright (C) 2005, 2006, 2008 Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
3
   This file is part of the GNU C Library.
4
4
5
   The GNU C Library is free software; you can redistribute it and/or
5
   The GNU C Library is free software; you can redistribute it and/or
Lines 143-175 Link Here
143
	stfd	fp30,_UC_FREGS+(30*8)(r3)
143
	stfd	fp30,_UC_FREGS+(30*8)(r3)
144
	stfd	fp31,_UC_FREGS+(31*8)(r3)
144
	stfd	fp31,_UC_FREGS+(31*8)(r3)
145
	stfd	fp0,_UC_FREGS+(32*8)(r3)
145
	stfd	fp0,_UC_FREGS+(32*8)(r3)
146
	
146
147
# ifdef __CONTEXT_ENABLE_VRS
147
# ifdef PIC
148
#  ifdef PIC
149
	mflr    r8
148
	mflr    r8
150
#   ifdef HAVE_ASM_PPC_REL16
149
#  ifdef HAVE_ASM_PPC_REL16
151
	bcl	20,31,1f
150
	bcl	20,31,1f
152
1:	mflr	r7
151
1:	mflr	r7
153
	addis	r7,r7,_GLOBAL_OFFSET_TABLE_-1b@ha
152
	addis	r7,r7,_GLOBAL_OFFSET_TABLE_-1b@ha
154
	addi	r7,r7,_GLOBAL_OFFSET_TABLE_-1b@l
153
	addi	r7,r7,_GLOBAL_OFFSET_TABLE_-1b@l
155
#   else
154
#  else
156
	bl      _GLOBAL_OFFSET_TABLE_@local-4
155
	bl      _GLOBAL_OFFSET_TABLE_@local-4
157
	mflr    r7
156
	mflr    r7
158
#   endif
157
#  endif
159
#   ifdef SHARED
158
#  ifdef SHARED
160
	lwz     r7,_rtld_global_ro@got(r7)
159
	lwz     r7,_rtld_global_ro@got(r7)
161
	mtlr    r8
160
	mtlr    r8
162
	lwz     r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
161
	lwz     r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
163
#   else
162
#  else
164
	lwz     r7,_dl_hwcap@got(r7)
163
	lwz     r7,_dl_hwcap@got(r7)
165
	mtlr    r8
164
	mtlr    r8
166
	lwz     r7,0(r7)
165
	lwz     r7,0(r7)
167
#   endif
166
#  endif
168
#  else
167
# else
169
	lis	r7,_dl_hwcap@ha
168
	lis	r7,_dl_hwcap@ha
170
	lwz     r7,_dl_hwcap@l(r7)
169
	lwz     r7,_dl_hwcap@l(r7)
171
#  endif
170
# endif
172
	andis.	r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
171
172
# ifdef __CONTEXT_ENABLE_VRS
173
	andis.	r6,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
173
174
174
	la	r10,(_UC_VREGS)(r3)
175
	la	r10,(_UC_VREGS)(r3)
175
	la	r9,(_UC_VREGS+16)(r3)
176
	la	r9,(_UC_VREGS+16)(r3)
Lines 425-431 Link Here
425
	/* Restore the floating-point registers */
426
	/* Restore the floating-point registers */
426
	lfd	fp31,_UC_FREGS+(32*8)(r31)
427
	lfd	fp31,_UC_FREGS+(32*8)(r31)
427
	lfd	fp0,_UC_FREGS+(0*8)(r31)
428
	lfd	fp0,_UC_FREGS+(0*8)(r31)
428
	mtfsf	0xff,fp31
429
# if defined _ARCH_PWR6
430
	/* Use the extended four-operand version of the mtfsf insn.  */
431
	mtfsf  0xff,fp0,1,0
432
# else
433
	/* Availability of DFP indicates a 64-bit FPSCR.  */
434
	andi.	r6,r7,PPC_FEATURE_HAS_DFP
435
	bne	7f
436
	/* Use the extended four-operand version of the mtfsf insn.  */
437
	mtfsf	0xff,fp31,1,0
438
	b	8f
439
	/* Continue to operate on the FPSCR as if it were 32-bits.  */
440
7:	mtfsf	0xff,fp31
441
8:
442
#endif /* _ARCH_PWR6 */
429
	lfd	fp1,_UC_FREGS+(1*8)(r31)
443
	lfd	fp1,_UC_FREGS+(1*8)(r31)
430
	lfd	fp2,_UC_FREGS+(2*8)(r31)
444
	lfd	fp2,_UC_FREGS+(2*8)(r31)
431
	lfd	fp3,_UC_FREGS+(3*8)(r31)
445
	lfd	fp3,_UC_FREGS+(3*8)(r31)
(-)glibc/sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/setcontext.S (+2 lines)
Line 0 Link Here
1
#define _ARCH_PWR6
2
#include_next <setcontext.S>
(-)glibc/sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/swapcontext.S (+2 lines)
Line 0 Link Here
1
#define _ARCH_PWR6
2
#include_next <swapcontext.S>
(-)glibc/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S (-10 / +48 lines)
Lines 1-5 Link Here
1
/* Switch to context.
1
/* Switch to context.
2
   Copyright (C) 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
2
   Copyright (C) 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
3
   This file is part of the GNU C Library.
4
4
5
   The GNU C Library is free software; you can redistribute it and/or
5
   The GNU C Library is free software; you can redistribute it and/or
Lines 27-32 Link Here
27
#include "ucontext_i.h"
27
#include "ucontext_i.h"
28
#include <asm/errno.h>
28
#include <asm/errno.h>
29
29
30
	.section	".toc","aw"
31
.LC__dl_hwcap:
32
#ifdef SHARED
33
	.tc _rtld_global_ro[TC],_rtld_global_ro
34
#else
35
	.tc _dl_hwcap[TC],_dl_hwcap
36
#endif
37
	.section ".text"
38
30
#if SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)
39
#if SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)
31
ENTRY(__novec_setcontext)
40
ENTRY(__novec_setcontext)
32
	CALL_MCOUNT 1
41
	CALL_MCOUNT 1
Lines 62-71 Link Here
62
  cmpdi r3,0
71
  cmpdi r3,0
63
  bne   L(nv_error_exit)
72
  bne   L(nv_error_exit)
64
73
74
# ifdef SHARED
75
/* Load _rtld-global._dl_hwcap.  */
76
  ld    r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r5)
77
# else
78
  ld    r5,0(r5) /* Load extern _dl_hwcap.  */
79
# endif
80
65
  lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
81
  lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
66
  lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
82
  lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
67
  lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
83
  lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
84
85
# if defined _ARCH_PWR6
86
  /* Use the extended four-operand version of the mtfsf insn.  */
87
  mtfsf  0xff,fp0,1,0
88
# else
89
  /* Availability of DFP indicates a 64-bit FPSCR.  */
90
  andi.  r6,r5,PPC_FEATURE_HAS_DFP
91
  bne    5f
92
  /* Use the extended four-operand version of the mtfsf insn.  */
93
  mtfsf  0xff,fp0,1,0
94
  b      6f
95
  /* Continue to operate on the FPSCR as if it were 32-bits.  */
96
5:
68
  mtfsf  0xff,fp0
97
  mtfsf  0xff,fp0
98
6:
99
# endif /* _ARCH_PWR6 */
69
  lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
100
  lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
70
  lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
101
  lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
71
  lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
102
  lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
Lines 189-203 Link Here
189
220
190
#endif
221
#endif
191
222
192
	.section	".toc","aw"
193
.LC__dl_hwcap:
194
#ifdef SHARED
195
	.tc _rtld_global_ro[TC],_rtld_global_ro
196
#else
197
	.tc _dl_hwcap[TC],_dl_hwcap
198
#endif
199
	.section ".text"
223
	.section ".text"
200
201
	.machine	"altivec"
224
	.machine	"altivec"
202
ENTRY(__setcontext)
225
ENTRY(__setcontext)
203
	CALL_MCOUNT 1
226
	CALL_MCOUNT 1
Lines 241-247 Link Here
241
# else
264
# else
242
  ld    r5,0(r5) /* Load extern _dl_hwcap.  */
265
  ld    r5,0(r5) /* Load extern _dl_hwcap.  */
243
# endif
266
# endif
244
  andis.  r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
267
  andis.  r6,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
245
  beq   L(has_no_vec)
268
  beq   L(has_no_vec)
246
269
247
  cmpdi r10,0
270
  cmpdi r10,0
Lines 346-352 Link Here
346
  lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
369
  lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
347
  lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
370
  lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
348
  lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
371
  lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
372
373
# if defined _ARCH_PWR6
374
  /* Use the extended four-operand version of the mtfsf insn.  */
375
  mtfsf  0xff,fp0,1,0
376
# else
377
  /* Availability of DFP indicates a 64-bit FPSCR.  */
378
  andi.  r6,r5,PPC_FEATURE_HAS_DFP
379
  bne    7f
380
  /* Use the extended four-operand version of the mtfsf insn.  */
381
  mtfsf  0xff,fp0,1,0
382
  b      8f
383
  /* Continue to operate on the FPSCR as if it were 32-bits.  */
384
7:
349
  mtfsf  0xff,fp0
385
  mtfsf  0xff,fp0
386
8:
387
# endif /* _ARCH_PWR6 */
350
  lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
388
  lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
351
  lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
389
  lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
352
  lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
390
  lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
(-)glibc/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S (-11 / +47 lines)
Lines 1-5 Link Here
1
/* Save current context and install the given one.
1
/* Save current context and install the given one.
2
   Copyright (C) 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
2
   Copyright (C) 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
3
   This file is part of the GNU C Library.
4
4
5
   The GNU C Library is free software; you can redistribute it and/or
5
   The GNU C Library is free software; you can redistribute it and/or
Lines 27-33 Link Here
27
#include "ucontext_i.h"
27
#include "ucontext_i.h"
28
#include <asm/errno.h>
28
#include <asm/errno.h>
29
29
30
	.section	".toc","aw"
31
.LC__dl_hwcap:
32
#ifdef SHARED
33
	.tc _rtld_global_ro[TC],_rtld_global_ro
34
#else
35
	.tc _dl_hwcap[TC],_dl_hwcap
36
#endif
37
30
#if SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)
38
#if SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)
39
	.section	".text"
31
ENTRY(__novec_swapcontext)
40
ENTRY(__novec_swapcontext)
32
	CALL_MCOUNT 2
41
	CALL_MCOUNT 2
33
#ifdef __ASSUME_NEW_RT_SIGRETURN_SYSCALL
42
#ifdef __ASSUME_NEW_RT_SIGRETURN_SYSCALL
Lines 157-166 Link Here
157
  cmpdi r0,0
166
  cmpdi r0,0
158
  bne	  L(nv_do_sigret)
167
  bne	  L(nv_do_sigret)
159
168
169
# ifdef SHARED
170
/* Load _rtld-global._dl_hwcap.  */
171
  ld    r8,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r8)
172
# else
173
  ld    r8,0(r8) /* Load extern _dl_hwcap.  */
174
# endif
175
160
  lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
176
  lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
161
  lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
177
  lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
162
  lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
178
  lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
179
# if defined _ARCH_PWR6
180
  /* Use the extended four-operand version of the mtfsf insn.  */
181
  mtfsf  0xff,fp0,1,0
182
# else
183
  /* Availability of DFP indicates a 64-bit FPSCR.  */
184
  andi.  r6,r8,PPC_FEATURE_HAS_DFP
185
  bne    5f
186
  /* Use the extended four-operand version of the mtfsf insn.  */
187
  mtfsf  0xff,fp0,1,0
188
  b      6f
189
  /* Continue to operate on the FPSCR as if it were 32-bits.  */
190
5:
163
  mtfsf  0xff,fp0
191
  mtfsf  0xff,fp0
192
6:
193
#endif /* _ARCH_PWR6 */
164
  lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
194
  lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
165
  lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
195
  lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
166
  lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
196
  lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
Lines 283-297 Link Here
283
313
284
#endif
314
#endif
285
315
286
	.section	".toc","aw"
287
.LC__dl_hwcap:
288
#ifdef SHARED
289
	.tc _rtld_global_ro[TC],_rtld_global_ro
290
#else
291
	.tc _dl_hwcap[TC],_dl_hwcap
292
#endif
293
	.section ".text"
316
	.section ".text"
294
295
	.machine	"altivec"
317
	.machine	"altivec"
296
ENTRY(__swapcontext)
318
ENTRY(__swapcontext)
297
	CALL_MCOUNT 2
319
	CALL_MCOUNT 2
Lines 409-415 Link Here
409
  la    r10,(SIGCONTEXT_V_RESERVE+8)(r3)
431
  la    r10,(SIGCONTEXT_V_RESERVE+8)(r3)
410
  la    r9,(SIGCONTEXT_V_RESERVE+24)(r3)
432
  la    r9,(SIGCONTEXT_V_RESERVE+24)(r3)
411
433
412
  andis.  r8,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
434
  andis.  r6,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
413
435
414
  clrrdi  r10,r10,4
436
  clrrdi  r10,r10,4
415
  beq   L(has_no_vec)
437
  beq   L(has_no_vec)
Lines 540-546 Link Here
540
# else
562
# else
541
  ld    r8,0(r8) /* Load extern _dl_hwcap.  */
563
  ld    r8,0(r8) /* Load extern _dl_hwcap.  */
542
# endif
564
# endif
543
  andis.  r8,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
565
  andis.  r6,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
544
  beq   L(has_no_vec2)
566
  beq   L(has_no_vec2)
545
567
546
  cmpdi r10,0
568
  cmpdi r10,0
Lines 646-652 Link Here
646
  lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
668
  lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
647
  lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
669
  lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
648
  lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
670
  lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
671
# if defined _ARCH_PWR6
672
  /* Use the extended four-operand version of the mtfsf insn.  */
673
  mtfsf  0xff,fp0,1,0
674
# else
675
  /* Availability of DFP indicates a 64-bit FPSCR.  */
676
  andi.  r6,r8,PPC_FEATURE_HAS_DFP
677
  bne    7f
678
  /* Use the extended four-operand version of the mtfsf insn.  */
679
  mtfsf  0xff,fp0,1,0
680
  b      8f
681
  /* Continue to operate on the FPSCR as if it were 32-bits.  */
682
7:
649
  mtfsf  0xff,fp0
683
  mtfsf  0xff,fp0
684
8:
685
#endif /* _ARCH_PWR6 */
650
  lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
686
  lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
651
  lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
687
  lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
652
  lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
688
  lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)

Return to bug 6411