View | Details | Raw Unified | Return to bug 6411 | Differences between
and this patch

Collapse All | Expand All

(-)glibc/sysdeps/powerpc/elf/rtld-global-offsets.sym (-2 / +2 lines)
Lines 2-7 Link Here
2
2
3
#include <ldsodefs.h>
3
#include <ldsodefs.h>
4
4
5
#define rtdl_global_ro_offsetof(mem) offsetof (struct rtld_global_ro, mem)
5
#define rtld_global_ro_offsetof(mem) offsetof (struct rtld_global_ro, mem)
6
6
7
RTLD_GLOBAL_RO_DL_HWCAP_OFFSET	rtdl_global_ro_offsetof (_dl_hwcap)
7
RTLD_GLOBAL_RO_DL_HWCAP_OFFSET	rtld_global_ro_offsetof (_dl_hwcap)
(-)glibc/sysdeps/powerpc/fpscr.h (+29 lines)
Line 0 Link Here
1
/* Macro to restore the entire FPSCR, short and long form.
2
   Copyright (C) 2008 Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
4
   Contributed by Ryan S. Arnold <rsa@us.ibm.com>
5
6
   The GNU C Library is free software; you can redistribute it and/or
7
   modify it under the terms of the GNU Lesser General Public
8
   License as published by the Free Software Foundation; either
9
   version 2.1 of the License, or (at your option) any later version.
10
11
   The GNU C Library is distributed in the hope that it will be useful,
12
   but WITHOUT ANY WARRANTY; without even the implied warranty of
13
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
   Lesser General Public License for more details.
15
16
   You should have received a copy of the GNU Lesser General Public
17
   License along with the GNU C Library; if not, write to the Free
18
   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
19
   02111-1307 USA.  */
20
21
#if defined _ARCH_PWR6
22
 /* On Power6[x] four operands are required with the 'L' field
23
  * equal to '1' in order to copy the entirety of 'reg' into the
24
  * full 64-bit wide FPSCR.  The field mask and 'W' field are
25
  * ignored when L is '1'.  */
26
# define RESTORE_FPSCR(reg) mtfsf	0xff, (reg), 1, 0
27
#else /* _ARCH_PWR6 */
28
# define RESTORE_FPSCR(reg) mtfsf	0xff, (reg)
29
#endif /* _ARCH_PWR6 */
(-)glibc/sysdeps/powerpc/fpu/Implies (+1 lines)
Line 0 Link Here
1
powerpc/math
(-)glibc/sysdeps/powerpc/fpu/feholdexcpt.c (-2 / +4 lines)
Lines 1-5 Link Here
1
/* Store current floating-point environment and clear exceptions.
1
/* Store current floating-point environment and clear exceptions.
2
   Copyright (C) 1997, 2005 Free Software Foundation, Inc.
2
   Copyright (C) 1997, 2005, 2008 Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
3
   This file is part of the GNU C Library.
4
4
5
   The GNU C Library is free software; you can redistribute it and/or
5
   The GNU C Library is free software; you can redistribute it and/or
Lines 18-23 Link Here
18
   02111-1307 USA.  */
18
   02111-1307 USA.  */
19
19
20
#include <fenv_libc.h>
20
#include <fenv_libc.h>
21
#include <fpu_control.h>
22
#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM)
21
23
22
int
24
int
23
feholdexcept (fenv_t *envp)
25
feholdexcept (fenv_t *envp)
Lines 35-41 Link Here
35
  /* If the old env had any eabled exceptions, then mask SIGFPE in the
37
  /* If the old env had any eabled exceptions, then mask SIGFPE in the
36
     MSR FE0/FE1 bits.  This may allow the FPU to run faster because it
38
     MSR FE0/FE1 bits.  This may allow the FPU to run faster because it
37
     always takes the default action and can not generate SIGFPE. */
39
     always takes the default action and can not generate SIGFPE. */
38
  if ((old.l[1] & 0x000000F8) != 0)
40
  if ((old.l[1] & _FPU_MASK_ALL) != 0)
39
    (void)__fe_mask_env ();
41
    (void)__fe_mask_env ();
40
42
41
  /* Put the new state in effect.  */
43
  /* Put the new state in effect.  */
(-)glibc/sysdeps/powerpc/fpu/fenv_libc.h (-2 / +23 lines)
Lines 32-40 Link Here
32
#define fegetenv_register() \
32
#define fegetenv_register() \
33
        ({ fenv_t env; asm volatile ("mffs %0" : "=f" (env)); env; })
33
        ({ fenv_t env; asm volatile ("mffs %0" : "=f" (env)); env; })
34
34
35
/* Power6[x] provides a 64-bit FPSCR.  */
36
#if defined _ARCH_PWR6
37
# define fesetenv_register(env) \
38
        ({ double d = (env); asm volatile ("mtfsf 0xff,%0,1,0" : : "f" (d)); })
39
#else /* _ARCH_PWR6 */
35
/* Equivalent to fesetenv, but takes a fenv_t instead of a pointer.  */
40
/* Equivalent to fesetenv, but takes a fenv_t instead of a pointer.  */
36
#define fesetenv_register(env) \
41
# define fesetenv_register(env) \
37
        ({ double d = (env); asm volatile ("mtfsf 0xff,%0" : : "f" (d)); })
42
        ({ double d = (env); asm volatile ("mtfsf 0xff,%0" : : "f" (d)); })
43
#endif /* _ARCH_PWR6 */
38
44
39
/* This very handy macro:
45
/* This very handy macro:
40
   - Sets the rounding mode to 'round to nearest';
46
   - Sets the rounding mode to 'round to nearest';
Lines 42-48 Link Here
42
   - Prevents exceptions from being raised for inexact results.
48
   - Prevents exceptions from being raised for inexact results.
43
   These things happen to be exactly what you need for typical elementary
49
   These things happen to be exactly what you need for typical elementary
44
   functions.  */
50
   functions.  */
45
#define relax_fenv_state() asm ("mtfsfi 7,0")
51
#if defined _ARCH_PWR6
52
/* - Sets the decimal rounding mode to 'round to nearest';  */
53
# define relax_fenv_state() \
54
       ({ asm ("mtfsfi 7,0,1"); asm("mtfsfi 7,0"); })
55
#else /* _ARCH_PWR6 */
56
# define relax_fenv_state() asm ("mtfsfi 7,0")
57
#endif /* _ARCH_PWR6 */
46
58
47
/* Set/clear a particular FPSCR bit (for instance,
59
/* Set/clear a particular FPSCR bit (for instance,
48
   reset_fpscr_bit(FPSCR_VE);
60
   reset_fpscr_bit(FPSCR_VE);
Lines 122-131 Link Here
122
  FPSCR_UE,        /* underflow exception enable */
134
  FPSCR_UE,        /* underflow exception enable */
123
  FPSCR_ZE,        /* zero divide exception enable */
135
  FPSCR_ZE,        /* zero divide exception enable */
124
  FPSCR_XE,        /* inexact exception enable */
136
  FPSCR_XE,        /* inexact exception enable */
137
#if defined _ARCH_PWR6
138
  FPSCR_29,        /* Reserved on POWER6 */
139
#else /* _ARCH_PWR6 */
125
  FPSCR_NI         /* non-IEEE mode (typically, no denormalised numbers) */
140
  FPSCR_NI         /* non-IEEE mode (typically, no denormalised numbers) */
141
#endif /* _ARCH_PWR6 */
126
  /* the remaining two least-significant bits keep the rounding mode */
142
  /* the remaining two least-significant bits keep the rounding mode */
127
};
143
};
128
144
145
#if defined _ARCH_PWR6
146
  /* Not supported on POWER6.  Provided for source compat only.  */
147
# define FPSCR_NI 29
148
#endif /* _ARCH_PWR6 */
149
129
/* This operation (i) sets the appropriate FPSCR bits for its
150
/* This operation (i) sets the appropriate FPSCR bits for its
130
   parameter, (ii) converts SNaN to the corresponding NaN, and (iii)
151
   parameter, (ii) converts SNaN to the corresponding NaN, and (iii)
131
   otherwise passes its parameter through unchanged (in particular, -0
152
   otherwise passes its parameter through unchanged (in particular, -0
(-)glibc/sysdeps/powerpc/fpu/fesetenv.c (-8 / +11 lines)
Lines 1-5 Link Here
1
/* Install given floating-point environment.
1
/* Install given floating-point environment.
2
   Copyright (C) 1997,99,2000,01,02,07 Free Software Foundation, Inc.
2
   Copyright (C) 1997,1999-2002,2007,2008 Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
3
   This file is part of the GNU C Library.
4
4
5
   The GNU C Library is free software; you can redistribute it and/or
5
   The GNU C Library is free software; you can redistribute it and/or
Lines 18-25 Link Here
18
   02111-1307 USA.  */
18
   02111-1307 USA.  */
19
19
20
#include <fenv_libc.h>
20
#include <fenv_libc.h>
21
#include <fpu_control.h>
21
#include <bp-sym.h>
22
#include <bp-sym.h>
22
23
24
#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM)
25
23
int
26
int
24
__fesetenv (const fenv_t *envp)
27
__fesetenv (const fenv_t *envp)
25
{
28
{
Lines 29-46 Link Here
29
  new.fenv = *envp;
32
  new.fenv = *envp;
30
  old.fenv = fegetenv_register ();
33
  old.fenv = fegetenv_register ();
31
  
34
  
32
  /* If the old env has no eabled exceptions and the new env has any enabled
35
  /* If the old env has no enabled exceptions and the new env has any enabled
33
     exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits.  This will put
36
     exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits.  This will put the
34
     the hardware into "precise mode" and may cause the FPU to run slower on
37
     hardware into "precise mode" and may cause the FPU to run slower on some
35
     some hardware.  */
38
     hardware.  */
36
  if ((old.l[1] & 0x000000F8) == 0 && (new.l[1] & 0x000000F8) != 0)
39
  if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0)
37
    (void)__fe_nomask_env ();
40
    (void)__fe_nomask_env ();
38
  
41
  
39
  /* If the old env had any eabled exceptions and the new env has no enabled
42
  /* If the old env had any enabled exceptions and the new env has no enabled
40
     exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
43
     exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
41
     FPU to run faster because it always takes the default action and can not 
44
     FPU to run faster because it always takes the default action and can not 
42
     generate SIGFPE. */
45
     generate SIGFPE. */
43
  if ((old.l[1] & 0x000000F8) != 0 && (new.l[1] & 0x000000F8) == 0)
46
  if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0)
44
    (void)__fe_mask_env ();
47
    (void)__fe_mask_env ();
45
    
48
    
46
  fesetenv_register (*envp);
49
  fesetenv_register (*envp);
(-)glibc/sysdeps/powerpc/fpu/feupdateenv.c (-3 / +6 lines)
Lines 1-5 Link Here
1
/* Install given floating-point environment and raise exceptions.
1
/* Install given floating-point environment and raise exceptions.
2
   Copyright (C) 1997,99,2000,01,07 Free Software Foundation, Inc.
2
   Copyright (C) 1997,1999-2001,2007,2008 Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
3
   This file is part of the GNU C Library.
4
   Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997.
4
   Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997.
5
5
Lines 19-26 Link Here
19
   02111-1307 USA.  */
19
   02111-1307 USA.  */
20
20
21
#include <fenv_libc.h>
21
#include <fenv_libc.h>
22
#include <fpu_control.h>
22
#include <bp-sym.h>
23
#include <bp-sym.h>
23
24
25
#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM)
26
24
int
27
int
25
__feupdateenv (const fenv_t *envp)
28
__feupdateenv (const fenv_t *envp)
26
{
29
{
Lines 39-52 Link Here
39
     exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits.  This will put
42
     exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits.  This will put
40
     the hardware into "precise mode" and may cause the FPU to run slower on
43
     the hardware into "precise mode" and may cause the FPU to run slower on
41
     some hardware.  */
44
     some hardware.  */
42
  if ((old.l[1] & 0x000000F8) == 0 && (new.l[1] & 0x000000F8) != 0)
45
  if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0)
43
    (void)__fe_nomask_env ();
46
    (void)__fe_nomask_env ();
44
  
47
  
45
  /* If the old env had any eabled exceptions and the new env has no enabled
48
  /* If the old env had any eabled exceptions and the new env has no enabled
46
     exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
49
     exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
47
     FPU to run faster because it always takes the default action and can not 
50
     FPU to run faster because it always takes the default action and can not 
48
     generate SIGFPE. */
51
     generate SIGFPE. */
49
  if ((old.l[1] & 0x000000F8) != 0 && (new.l[1] & 0x000000F8) == 0)
52
  if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0)
50
    (void)__fe_mask_env ();
53
    (void)__fe_mask_env ();
51
54
52
  /* Atomically enable and raise (if appropriate) exceptions set in `new'. */
55
  /* Atomically enable and raise (if appropriate) exceptions set in `new'. */
(-)glibc/sysdeps/powerpc/fpu/fpu_control.h (-23 / +87 lines)
Lines 1-5 Link Here
1
/* FPU control word definitions.  PowerPC version.
1
/* FPU control word definitions.  PowerPC version.
2
   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
2
   Copyright (C) 1996, 1997, 1998, 2008 Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
3
   This file is part of the GNU C Library.
4
4
5
   The GNU C Library is free software; you can redistribute it and/or
5
   The GNU C Library is free software; you can redistribute it and/or
Lines 20-67 Link Here
20
#ifndef _FPU_CONTROL_H
20
#ifndef _FPU_CONTROL_H
21
#define _FPU_CONTROL_H
21
#define _FPU_CONTROL_H
22
22
23
/* rounding control */
23
#include <stdbool.h>
24
25
/* Provided by libc on application start.  */
26
extern bool __ppc_feature_dfp_available;
27
28
/* Binary float rounding control.  */
24
#define _FPU_RC_NEAREST 0x00   /* RECOMMENDED */
29
#define _FPU_RC_NEAREST 0x00   /* RECOMMENDED */
25
#define _FPU_RC_DOWN    0x03
30
#define _FPU_RC_DOWN    0x03
26
#define _FPU_RC_UP      0x02
31
#define _FPU_RC_UP      0x02
27
#define _FPU_RC_ZERO    0x01
32
#define _FPU_RC_ZERO    0x01
28
33
29
#define _FPU_MASK_NI  0x04 /* non-ieee mode */
34
/* Masks of interrupt enable bits.  */
30
31
/* masking of interrupts */
32
#define _FPU_MASK_ZM  0x10 /* zero divide */
35
#define _FPU_MASK_ZM  0x10 /* zero divide */
33
#define _FPU_MASK_OM  0x40 /* overflow */
36
#define _FPU_MASK_OM  0x40 /* overflow */
34
#define _FPU_MASK_UM  0x20 /* underflow */
37
#define _FPU_MASK_UM  0x20 /* underflow */
35
#define _FPU_MASK_XM  0x08 /* inexact */
38
#define _FPU_MASK_XM  0x08 /* inexact */
36
#define _FPU_MASK_IM  0x80 /* invalid operation */
39
#define _FPU_MASK_IM  0x80 /* invalid operation */
37
40
38
#define _FPU_RESERVED 0xffffff00 /* These bits are reserved are not changed. */
41
/* The fdlibm code requires no interrupts for exceptions.  On POWER6[x]
39
42
 * hardware this implicitly sets the default decimal rounding mode
40
/* The fdlibm code requires no interrupts for exceptions.  */
43
 * to _FPU_DEC_RC_NEAREST as well.  */
41
#define _FPU_DEFAULT  0x00000000 /* Default value.  */
44
#define _FPU_DEFAULT  0x00000000 /* Default value.  */
42
45
43
/* IEEE:  same as above, but (some) exceptions;
46
/* IEEE:  same as above, but (some) exceptions;
44
   we leave the 'inexact' exception off.
47
   we leave the 'inexact' exception off.  */
45
 */
46
#define _FPU_IEEE     0x000000f0
48
#define _FPU_IEEE     0x000000f0
47
49
48
/* Type of the control word.  */
50
/* Type of the control word.  */
49
typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
51
typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
50
52
51
/* Macros for accessing the hardware control word.  */
53
/* Mask of the DRN + reserved bit 28 of the 64-bit FPSCR as defined by ISA
52
#define _FPU_GETCW(__cw) ( { \
54
 * 2.05.  */
53
  union { double d; fpu_control_t cw[2]; } \
55
#define __DRN_MASK				0xf
54
    tmp __attribute__ ((__aligned__(8))); \
56
55
  __asm__ ("mffs 0; stfd%U0 0,%0" : "=m" (tmp.d) : : "fr0"); \
57
/* ISA 2.05 defines a 64-bit FPSCR.  Under ISA 2.05 decimal rounding modes are
56
  (__cw)=tmp.cw[1]; \
58
 * a part of the optional DFP category.  If this category is not implemented
59
 * then the bits are reserved and operations against them are no-ops.  */
60
#if defined _ARCH_PWR6
61
  /* We appropriate bits 28-31 of the fpu_control_t for the DRN (decimal
62
   * rounding control field).  ISA 2.05 reserves bit 28 of the 64-bit FPSCR
63
   * for future decimal rounding modes so we'll reserve bit 31 of the
64
   * fpu_control_t as well. */
65
# define _FPU_DEC_RC_NEAREST			0x00000000
66
# define _FPU_DEC_RC_TOWARDZERO			0x10000000
67
# define _FPU_DEC_RC_UPWARD			0x20000000
68
# define _FPU_DEC_RC_DOWNWARD			0x30000000
69
# define _FPU_DEC_RC_NEARESTFROMZERO		0x40000000
70
71
  /* The following Decimal Rounding Modes are supported by POWER6[x] hardware
72
   * but don't have equivalent ISO C Draft Technical Report rounding modes.  */
73
# define _FPU_DEC_RC_NEARESTTOWARDZERO		0x50000000
74
# define _FPU_DEC_RC_FROMZERO			0x60000000
75
# define _FPU_DEC_RC_PREPAREFORSHORTERPRECISION	0x70000000
76
77
  /* Non-IEEE mode Not available in ISA 2.05.  We no-op it for forward porting
78
   * compat since it is valid on some PowerPC processors.  */ 
79
# define _FPU_MASK_NI				0x00
80
81
  /* The DRN and the Binary Rounding Control bits are not reserved.  Non-IEEE
82
   * mode is NOT available in ISA 2.05 and is therefore reserved.  Bit 31 is
83
   * reserved for future decimal rounding mode expansion.  */
84
# define _FPU_RESERVED				0x8fffff04
85
86
#else /* _ARCH_PWR6 */
87
  /* Pre-ISA 2.05 */
88
# define _FPU_RESERVED 0xffffff00 /* These bits are reserved and not changed. */
89
# define _FPU_MASK_NI  0x04 /* non-ieee mode */
90
#endif /* _ARCH_PWR6 */
91
92
/* Macros for [gs]etting the fields of the FPSCR (32 or 64-bit) allowed by the
93
 * defined masks.  These macros check the hwcap for particular feature support
94
 * and will use the high 32-bits of the ISA 2.05 compliant 64-bit FPSCR as
95
 * necessary.  */
96
97
/* Note: Reserved bits in the fpu_control_t are undefined when the _FPU_GETCW
98
 * macro completes.  */
99
#define _FPU_GETCW(__cw) ( {						      \
100
  union { double d; fpu_control_t cw[2]; }				      \
101
    tmp __attribute__ ((__aligned__(8)));				      \
102
  __asm__ ("mffs 0; stfd%U0 0,%0" : "=m" (tmp.d) : : "fr0");		      \
103
  if(__ppc_feature_dfp_available == true)				      \
104
    /* Shift FPSCR DRN values to fpu_control_t DRN.  */			      \
105
    tmp.cw[1]=(((tmp.cw[0]&__DRN_MASK) << 28) | tmp.cw[1]);		      \
106
  (__cw)=tmp.cw[1];							      \
57
  tmp.cw[1]; } )
107
  tmp.cw[1]; } )
58
#define _FPU_SETCW(__cw) { \
108
59
  union { double d; fpu_control_t cw[2]; } \
109
#define _FPU_SETCW(__cw) {						      \
60
    tmp __attribute__ ((__aligned__(8))); \
110
  union { double d; fpu_control_t cw[2]; }				      \
61
  tmp.cw[0] = 0xFFF80000; /* More-or-less arbitrary; this is a QNaN. */ \
111
    tmp __attribute__ ((__aligned__(8)));				      \
62
  tmp.cw[1] = __cw; \
112
  if(__ppc_feature_dfp_available == true)				      \
63
  __asm__ ("lfd%U0 0,%0; mtfsf 255,0" : : "m" (tmp.d) : "fr0"); \
113
    {									      \
64
}
114
      /* Shift fpu_control_t DRN values to the FPSCR DRN.  */		      \
115
      /* Shortcut since we know 4-31 of cw[1] are reserved.  */		      \
116
      tmp.cw[0] = __cw>>28;						      \
117
      /* Clear the DRN bits out of the low 32.  */			      \
118
      tmp.cw[1] = (~(__DRN_MASK<<28))&__cw;				      \
119
      /* Set the entire 64-bit FPSCR.  */				      \
120
      __asm__ ("lfd%U0 0,%0; mtfsf 255,0,1,0" : : "m" (tmp.d) : "fr0");	      \
121
    } else {								      \
122
      /* Otherwise we either have a 32-bit FPSCR or we don't have  */	      \
123
      /* PPC_FEATURE_HAS_DFP and don't care about the state of the  */	      \
124
      /* high 32-bits since it would be reserved and undefined.  */	      \
125
      tmp.cw[0] = 0x00000000;						      \
126
      tmp.cw[1] = __cw;							      \
127
      __asm__ ("lfd%U0 0,%0; mtfsf 255,0" : : "m" (tmp.d) : "fr0");	      \
128
    } }
65
129
66
/* Default control word set at startup.  */
130
/* Default control word set at startup.  */
67
extern fpu_control_t __fpu_control;
131
extern fpu_control_t __fpu_control;
(-)glibc/sysdeps/powerpc/math/Makefile (+3 lines)
Line 0 Link Here
1
ifeq ($(subdir),math)
2
libm-tests += test-powerpc-fenv
3
endif
(-)glibc/sysdeps/powerpc/math/test-fpucw.c (+124 lines)
Line 0 Link Here
1
/* Test to verify proper save and restore of 64-bit fpu control word.
2
3
   Copyright (C) 2008 Free Software Foundation, Inc.
4
   This file is part of the GNU C Library.
5
   Contributed by Ryan S. Arnold <rsa@us.ibm.com>
6
7
   The GNU C Library is free software; you can redistribute it and/or
8
   modify it under the terms of the GNU Lesser General Public
9
   License as published by the Free Software Foundation; either
10
   version 2.1 of the License, or (at your option) any later version.
11
12
   The GNU C Library is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
   Lesser General Public License for more details.
16
17
   You should have received a copy of the GNU Lesser General Public
18
   License along with the GNU C Library; if not, write to the Free
19
   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20
   02111-1307 USA.  */
21
22
#include <fpu_control.h>
23
#include <stdio.h>
24
#include <dl-procinfo.h>
25
#include <ldsodefs.h>
26
#include <sysdep.h>
27
28
#if defined _ARCH_PWR6
29
typedef unsigned long long fpscr_t __attribute__ ((__mode__ (__DI__)));
30
31
# define _GETFPSCR(__fpscr) ({						      \
32
   union { double d;							      \
33
           fpscr_t fpscr; }						      \
34
     tmp __attribute__ ((__aligned__(8)));				      \
35
   __asm__ ("mffs 0; stfd%U0 0,%0" : "=m" (tmp.d) : : "fr0");		      \
36
   (__fpscr)=tmp.fpscr; })
37
38
  /* Some masks for a 64-bit FPSCR defined in ISA 2.05.  */
39
# define _FPSCR_RESERVED		0xfffffff8ffffff04ULL
40
# define _FPSCR_NODFP_RESERVED		0xffffffffffffff04ULL
41
# define _FPSCR_DEFAULT			0x0000000000000000ULL
42
# define _FPSCR_DEC_RC_TOWARDZERO	0x0000000100000000ULL
43
# define _FPSCR_RC_DOWN			0x0000000000000003ULL
44
#endif /* _ARCH_PWR6 */
45
46
int
47
main (void)
48
{
49
#ifdef _FPU_GETCW
50
  unsigned long int fpuct_expect;
51
  fpu_control_t initial_cw;
52
# if defined _ARCH_PWR6
53
  fpscr_t fpscr;
54
  unsigned long long int fpscr_expect;
55
  fpu_control_t new_cw = (_FPU_DEC_RC_TOWARDZERO | _FPU_RC_DOWN);
56
# else /* _ARCH_PWR6 */
57
  fpu_control_t new_cw = _FPU_RC_DOWN;
58
  fpuct_expect = ((_FPU_DEFAULT & ~_FPU_RESERVED) | _FPU_RC_DOWN);
59
# endif /* _ARCH_PWR6 */
60
61
  _FPU_GETCW (initial_cw);
62
63
  initial_cw &= ~_FPU_RESERVED;
64
65
  if (initial_cw != (_FPU_DEFAULT & ~_FPU_RESERVED))
66
    {
67
      printf ("initial control word is 0x%.8lx but should be 0x%.8lx.\n",
68
	      (unsigned long int) initial_cw,
69
	      (unsigned long int) (_FPU_DEFAULT & ~_FPU_RESERVED));
70
      return 1;
71
    }
72
73
  _FPU_SETCW(new_cw);
74
# if defined _ARCH_PWR6
75
76
  printf("__ppc_feature_dfp_available == %d\n", __ppc_feature_dfp_available);
77
  /* Category Decimal Floating-Point is an optional part of ISA 2.05 so this may
78
   * not be implemented.  We need to test at runtime and adjust our expected
79
   * results in accordance.  */
80
  if (__ppc_feature_dfp_available == true)
81
    {
82
      fpscr_expect = ((_FPSCR_DEFAULT & ~_FPSCR_RESERVED) | _FPSCR_DEC_RC_TOWARDZERO | _FPSCR_RC_DOWN);
83
      fpuct_expect = ((_FPU_DEFAULT & ~_FPU_RESERVED) | _FPU_DEC_RC_TOWARDZERO | _FPU_RC_DOWN);
84
    }
85
  else
86
    {
87
      /* Setting the _FPSCR_DEC_RC_TOWARDZERO bit will result in a nop.  */
88
      fpscr_expect = ((_FPSCR_DEFAULT & ~_FPSCR_NODFP_RESERVED) | _FPSCR_RC_DOWN);
89
90
      /* The _FPSCR_DEC_RC_TOWARDZERO bit wasn't set into the FPSCR so it won't
91
       * be fetched into the _FPU_DEC_RC_TOWARDZERO bit of the fpu_control_t.  */
92
      fpuct_expect = ((_FPU_DEFAULT & ~_FPU_RESERVED) | _FPU_RC_DOWN);
93
    }
94
95
  /* Verify that the results coming out of the FPSCR are consistent with what's
96
   * expected.  This validates the _FPU_SETCW macro.  */
97
  _GETFPSCR(fpscr);
98
99
  if (fpscr != (fpscr_expect))
100
    {
101
      printf ("FPSCR is 0x%.16llx but should be 0x%.16llx.\n",
102
	      (unsigned long long int) fpscr,
103
	      (unsigned long long int) fpscr_expect);
104
      return 1;
105
    }
106
107
  /* Now make sure that the _FPU_GETCW macro transfers the DRN in the FPSCR
108
   * to the DRN field in the fpu_control_t properly if the Decimal
109
   * Floating-Point category is implemented.  */
110
111
# endif /* _ARCH_PWR6 */
112
  new_cw = 0x00000000UL;
113
  _FPU_GETCW(new_cw);
114
115
  if (new_cw != fpuct_expect)
116
    {
117
      printf ("control word is 0x%.8lx but should be 0x%.8lx.\n",
118
	      (unsigned long int) new_cw,
119
	      (unsigned long int) (fpuct_expect));
120
      return 1;
121
    }
122
#endif /* _FPU_GETCW */
123
  return 0;
124
}
(-)glibc/sysdeps/powerpc/math/test-powerpc-fenv.c (+64 lines)
Line 0 Link Here
1
/* Tests to verify proper behavior of internal fenv functions which operate
2
   directly upon the 32 or 64 bit FPSCR.
3
4
   Copyright (C) 2008 Free Software Foundation, Inc.
5
   This file is part of the GNU C Library.
6
   Contributed by Ryan S. Arnold <rsa@us.ibm.com>
7
8
   The GNU C Library is free software; you can redistribute it and/or
9
   modify it under the terms of the GNU Lesser General Public
10
   License as published by the Free Software Foundation; either
11
   version 2.1 of the License, or (at your option) any later version.
12
13
   The GNU C Library is distributed in the hope that it will be useful,
14
   but WITHOUT ANY WARRANTY; without even the implied warranty of
15
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16
   Lesser General Public License for more details.
17
18
   You should have received a copy of the GNU Lesser General Public
19
   License along with the GNU C Library; if not, write to the Free
20
   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
21
   02111-1307 USA.  */
22
23
#include <fenv_libc.h>
24
#include <stdio.h>
25
26
int
27
main (void)
28
{
29
#if defined _ARCH_PWR6
30
  fenv_union_t fe;
31
  fenv_union_t orig;
32
  orig.fenv = fegetenv_register();
33
  fe.fenv = fegetenv_register();
34
35
  /* Set a decimal float rounding mode in the high order word.  */
36
  fe.l[0] |= 0x01;
37
38
  fesetenv_register(fe.fenv);
39
  fe.fenv = fegetenv_register();
40
41
  /* Make sure the high order bits are saved to the FPSCR and restored.  */
42
  if (fe.l[0] != (orig.l[0] | 0x01))
43
    {
44
      printf ("fenv_t highword is 0x%.8x but should be 0x%.8x.\n",
45
	      (unsigned int) fe.l[0],
46
	      (unsigned int) (orig.l[0] | 0x01));
47
      return 1;
48
    }
49
50
  relax_fenv_state();
51
  fe.fenv = fegetenv_register();
52
53
  /* Make sure the decimal rounding mode triple is 0x0 since '000' is decimal
54
   * round to nearest.  */
55
  if (fe.l[0] != 0x00)
56
    {
57
      printf ("fenv_t highword is 0x%.8x but should be 0x%.8x.\n",
58
	      (unsigned int) fe.l[0],
59
	      (unsigned int) 0x0);
60
      return 1;
61
    }
62
#endif /* _ARCH_PWR6 */
63
  return 0;
64
}
(-)glibc/sysdeps/unix/sysv/linux/powerpc/Versions (+3 lines)
Lines 1-4 Link Here
1
libc {
1
libc {
2
  GLIBC_2.9 {
3
    __ppc_feature_dfp_available;
4
  }
2
  GLIBC_PRIVATE {
5
  GLIBC_PRIVATE {
3
    __vdso_get_tbfreq;
6
    __vdso_get_tbfreq;
4
    __vdso_clock_gettime;
7
    __vdso_clock_gettime;
(-)glibc/sysdeps/unix/sysv/linux/powerpc/libc-start.c (-1 / +8 lines)
Lines 1-4 Link Here
1
/* Copyright (C) 1998, 2000, 2001, 2002, 2003, 2004, 2005, 2007
1
/* Copyright (C) 1998, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
2
   Free Software Foundation, Inc.
2
   Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
3
   This file is part of the GNU C Library.
4
4
Lines 23-31 Link Here
23
#include <sysdep.h>
23
#include <sysdep.h>
24
#include <bp-start.h>
24
#include <bp-start.h>
25
#include <bp-sym.h>
25
#include <bp-sym.h>
26
#include <stdbool.h>
26
27
27
28
28
int __cache_line_size attribute_hidden;
29
int __cache_line_size attribute_hidden;
30
31
/* Export the dfp feature available bit from the hwcap.  */
32
bool __ppc_feature_dfp_available;
33
29
/* The main work is done in the generic function.  */
34
/* The main work is done in the generic function.  */
30
#define LIBC_START_MAIN generic_start_main
35
#define LIBC_START_MAIN generic_start_main
31
#define LIBC_START_DISABLE_INLINE
36
#define LIBC_START_DISABLE_INLINE
Lines 87-92 Link Here
87
      case AT_DCACHEBSIZE:
92
      case AT_DCACHEBSIZE:
88
	__cache_line_size = av->a_un.a_val;
93
	__cache_line_size = av->a_un.a_val;
89
	break;
94
	break;
95
      case AT_HWCAP:
96
	__ppc_feature_dfp_available  = (av->a_un.a_val & PPC_FEATURE_HAS_DFP);
90
      }
97
      }
91
98
92
  return generic_start_main (stinfo->main, argc, ubp_av, auxvec,
99
  return generic_start_main (stinfo->main, argc, ubp_av, auxvec,
(-)glibc/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S (-2 / +4 lines)
Lines 1-5 Link Here
1
/* Jump to a new context powerpc32 common.
1
/* Jump to a new context powerpc32 common.
2
   Copyright (C) 2005, 2006 Free Software Foundation, Inc.
2
   Copyright (C) 2005, 2006, 2008 Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
3
   This file is part of the GNU C Library.
4
4
5
   The GNU C Library is free software; you can redistribute it and/or
5
   The GNU C Library is free software; you can redistribute it and/or
Lines 27-32 Link Here
27
   Any archecture that implements the Vector unit is assumed to also 
27
   Any archecture that implements the Vector unit is assumed to also 
28
   implement the floating unit.  */
28
   implement the floating unit.  */
29
29
30
#include <fpscr.h>
31
30
/* Stack frame offsets.  */
32
/* Stack frame offsets.  */
31
#define _FRAME_BACKCHAIN	0
33
#define _FRAME_BACKCHAIN	0
32
#define _FRAME_LR_SAVE		4
34
#define _FRAME_LR_SAVE		4
Lines 199-205 Link Here
199
	/* Restore the floating-point registers */
201
	/* Restore the floating-point registers */
200
	lfd	fp31,_UC_FREGS+(32*8)(r31)
202
	lfd	fp31,_UC_FREGS+(32*8)(r31)
201
	lfd	fp0,_UC_FREGS+(0*8)(r31)
203
	lfd	fp0,_UC_FREGS+(0*8)(r31)
202
	mtfsf	0xff,fp31
204
	RESTORE_FPSCR (fp31)
203
	lfd	fp1,_UC_FREGS+(1*8)(r31)
205
	lfd	fp1,_UC_FREGS+(1*8)(r31)
204
	lfd	fp2,_UC_FREGS+(2*8)(r31)
206
	lfd	fp2,_UC_FREGS+(2*8)(r31)
205
	lfd	fp3,_UC_FREGS+(3*8)(r31)
207
	lfd	fp3,_UC_FREGS+(3*8)(r31)
(-)glibc/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S (-2 / +4 lines)
Lines 1-5 Link Here
1
/* Save current context and jump to a new context.
1
/* Save current context and jump to a new context.
2
   Copyright (C) 2005, 2006 Free Software Foundation, Inc.
2
   Copyright (C) 2005, 2006, 2008 Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
3
   This file is part of the GNU C Library.
4
4
5
   The GNU C Library is free software; you can redistribute it and/or
5
   The GNU C Library is free software; you can redistribute it and/or
Lines 27-32 Link Here
27
   Any archecture that implements the Vector unit is assumed to also 
27
   Any archecture that implements the Vector unit is assumed to also 
28
   implement the floating unit.  */
28
   implement the floating unit.  */
29
29
30
#include <fpscr.h>
31
30
/* Stack frame offsets.  */
32
/* Stack frame offsets.  */
31
#define _FRAME_BACKCHAIN	0
33
#define _FRAME_BACKCHAIN	0
32
#define _FRAME_LR_SAVE		4
34
#define _FRAME_LR_SAVE		4
Lines 425-431 Link Here
425
	/* Restore the floating-point registers */
427
	/* Restore the floating-point registers */
426
	lfd	fp31,_UC_FREGS+(32*8)(r31)
428
	lfd	fp31,_UC_FREGS+(32*8)(r31)
427
	lfd	fp0,_UC_FREGS+(0*8)(r31)
429
	lfd	fp0,_UC_FREGS+(0*8)(r31)
428
	mtfsf	0xff,fp31
430
	RESTORE_FPSCR (fp31)
429
	lfd	fp1,_UC_FREGS+(1*8)(r31)
431
	lfd	fp1,_UC_FREGS+(1*8)(r31)
430
	lfd	fp2,_UC_FREGS+(2*8)(r31)
432
	lfd	fp2,_UC_FREGS+(2*8)(r31)
431
	lfd	fp3,_UC_FREGS+(3*8)(r31)
433
	lfd	fp3,_UC_FREGS+(3*8)(r31)
(-)glibc/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S (-3 / +5 lines)
Lines 1-5 Link Here
1
/* Switch to context.
1
/* Switch to context.
2
   Copyright (C) 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
2
   Copyright (C) 2002, 2004-2006, 2008 Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
3
   This file is part of the GNU C Library.
4
4
5
   The GNU C Library is free software; you can redistribute it and/or
5
   The GNU C Library is free software; you can redistribute it and/or
Lines 27-32 Link Here
27
#include "ucontext_i.h"
27
#include "ucontext_i.h"
28
#include <asm/errno.h>
28
#include <asm/errno.h>
29
29
30
#include <fpscr.h>
31
30
#if SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)
32
#if SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)
31
ENTRY(__novec_setcontext)
33
ENTRY(__novec_setcontext)
32
	CALL_MCOUNT 1
34
	CALL_MCOUNT 1
Lines 65-71 Link Here
65
  lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
67
  lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
66
  lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
68
  lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
67
  lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
69
  lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
68
  mtfsf  0xff,fp0
70
  RESTORE_FPSCR (fp0)
69
  lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
71
  lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
70
  lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
72
  lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
71
  lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
73
  lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
Lines 346-352 Link Here
346
  lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
348
  lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
347
  lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
349
  lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
348
  lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
350
  lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
349
  mtfsf  0xff,fp0
351
  RESTORE_FPSCR (fp0)
350
  lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
352
  lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
351
  lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
353
  lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
352
  lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
354
  lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
(-)glibc/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S (-3 / +5 lines)
Lines 1-5 Link Here
1
/* Save current context and install the given one.
1
/* Save current context and install the given one.
2
   Copyright (C) 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
2
   Copyright (C) 2002, 2004-2006, 2008 Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
3
   This file is part of the GNU C Library.
4
4
5
   The GNU C Library is free software; you can redistribute it and/or
5
   The GNU C Library is free software; you can redistribute it and/or
Lines 27-32 Link Here
27
#include "ucontext_i.h"
27
#include "ucontext_i.h"
28
#include <asm/errno.h>
28
#include <asm/errno.h>
29
29
30
#include <fpscr.h>
31
30
#if SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)
32
#if SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)
31
ENTRY(__novec_swapcontext)
33
ENTRY(__novec_swapcontext)
32
	CALL_MCOUNT 2
34
	CALL_MCOUNT 2
Lines 160-166 Link Here
160
  lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
162
  lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
161
  lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
163
  lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
162
  lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
164
  lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
163
  mtfsf  0xff,fp0
165
  RESTORE_FPSCR (fp0)
164
  lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
166
  lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
165
  lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
167
  lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
166
  lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
168
  lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
Lines 646-652 Link Here
646
  lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
648
  lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
647
  lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
649
  lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
648
  lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
650
  lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
649
  mtfsf  0xff,fp0
651
  RESTORE_FPSCR (fp0)
650
  lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
652
  lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
651
  lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
653
  lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
652
  lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
654
  lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
(-)glibc/sysdeps/mach/hurd/powerpc/sigreturn.c (-1 / +5 lines)
Lines 1-5 Link Here
1
/* Return from signal handler for Hurd.  PowerPC version.
1
/* Return from signal handler for Hurd.  PowerPC version.
2
   Copyright (C) 1996,97,98,2001 Free Software Foundation, Inc.
2
   Copyright (C) 1996,97,98,2001,2008 Free Software Foundation, Inc.
3
   This file is part of the GNU C Library.
3
   This file is part of the GNU C Library.
4
4
5
   The GNU C Library is free software; you can redistribute it and/or
5
   The GNU C Library is free software; you can redistribute it and/or
Lines 91-97 Link Here
91
91
92
  /* Restore the floating-point control/status register.  */
92
  /* Restore the floating-point control/status register.  */
93
  asm volatile ("lfd 0,256(31)");
93
  asm volatile ("lfd 0,256(31)");
94
#if defined _ARCH_PWR6
95
  asm volatile ("mtfsf 0xff,0,1,0");
96
#else /* _ARCH_PWR6 */
94
  asm volatile ("mtfsf 0xff,0");
97
  asm volatile ("mtfsf 0xff,0");
98
#endif /* _ARCH_PWR6 */
95
99
96
  /* Restore floating-point registers. */
100
  /* Restore floating-point registers. */
97
  restore_fpr (0);
101
  restore_fpr (0);

Return to bug 6411