Attachment 13802 Details for Bug 28614 – Use `abort ()' instead of `assert (0)'

[patch] Use `abort ()' instead of `assert (0)'

aarch64-nnn-abort.patch (text/plain), 10.53 KB, created by Pekka Seppänen on 2021-11-22 13:25:48 UTC

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Creator: Pekka Seppänen

Created: 2021-11-22 13:25:48 UTC

Size: 10.53 KB

patch

obsolete

>diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
>index bbe4b683100..1a7d904f140 100644
>--- a/opcodes/aarch64-asm-2.c
>+++ b/opcodes/aarch64-asm-2.c
>@@ -893,6 +893,6 @@ aarch64_insert_operand (const aarch64_operand *self,
>       return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
>     case 220:
>       return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
>-    default: assert (0); abort ();
>+    default: abort ();
>     }
> }
>diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
>index fd5412aa38b..eb7d9381df4 100644
>--- a/opcodes/aarch64-asm.c
>+++ b/opcodes/aarch64-asm.c
>@@ -147,7 +147,7 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
> 	  insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);
> 	  break;
> 	default:
>-	  assert (0);
>+	  abort ();
> 	}
>     }
>   else if (inst->opcode->iclass == cryptosm3)
>@@ -185,7 +185,7 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
> 	  insert_field (FLD_H, code, reglane_index, 0);
> 	  break;
> 	default:
>-	  assert (0);
>+	  abort ();
> 	}
>     }
>   return true;
>@@ -229,7 +229,7 @@ aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
> 	case 2: value = 0xa; break;
> 	case 3: value = 0x6; break;
> 	case 4: value = 0x2; break;
>-	default: assert (0);
>+	default: abort ();
> 	}
>       break;
>     case 2:
>@@ -242,7 +242,7 @@ aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
>       value = 0x0;
>       break;
>     default:
>-      assert (0);
>+      abort ();
>     }
>   insert_field (FLD_opcode, code, value, 0);
> 
>@@ -315,7 +315,7 @@ aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
>       opcodeh2 = 0x2;
>       break;
>     default:
>-      assert (0);
>+      abort ();
>     }
>   insert_fields (code, QSsize, 0, 3, FLD_vldst_size, FLD_S, FLD_Q);
>   gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
>@@ -605,7 +605,7 @@ aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info,
> 	case AARCH64_OPND_QLF_S_S: value = 0; break;
> 	case AARCH64_OPND_QLF_S_D: value = 1; break;
> 	case AARCH64_OPND_QLF_S_Q: value = 2; break;
>-	default: assert (0);
>+	default: abort ();
> 	}
>       insert_field (FLD_ldst_size, code, value, 0);
>     }
>@@ -1372,7 +1372,7 @@ aarch64_ins_sme_za_hv_tiles (const aarch64_operand *self,
>       fld_zan_imm = regno;
>       break;
>     default:
>-      assert (0);
>+      abort ();
>     }
> 
>   insert_field (self->fields[0], code, fld_size, 0);
>@@ -1446,7 +1446,7 @@ aarch64_ins_sme_sm_za (const aarch64_operand *self,
>   else if (info->reg.regno == 'z')
>     fld_crm = 0x04; /* SVCRZA.  */
>   else
>-    assert (0);
>+    abort ();
> 
>   insert_field (self->fields[0], code, fld_crm, 0);
>   return true;
>@@ -1510,7 +1510,7 @@ aarch64_ins_sme_pred_reg_with_index (const aarch64_operand *self,
>       fld_tshl = 0x0;
>       break;
>     default:
>-      assert (0);
>+      abort ();
>   }
> 
>   insert_field (self->fields[2], code, fld_i1, 0);
>@@ -1544,7 +1544,7 @@ encode_asimd_fcvt (aarch64_inst *inst)
>       qualifier = inst->operands[0].qualifier;
>       break;
>     default:
>-      assert (0);
>+      abort ();
>     }
>   assert (qualifier == AARCH64_OPND_QLF_V_4S
> 	  || qualifier == AARCH64_OPND_QLF_V_2D);
>@@ -1749,7 +1749,7 @@ do_special_encoding (struct aarch64_inst *inst)
> 	case AARCH64_OPND_QLF_S_S: value = 0; break;
> 	case AARCH64_OPND_QLF_S_D: value = 1; break;
> 	case AARCH64_OPND_QLF_S_H: value = 3; break;
>-	default: assert (0);
>+	default: abort ();
> 	}
>       insert_field (FLD_type, &inst->value, value, 0);
>     }
>@@ -2098,13 +2098,13 @@ convert_mov_to_movewide (aarch64_inst *inst)
>       value = ~inst->operands[1].imm.value;
>       break;
>     default:
>-      assert (0);
>+      abort ();
>     }
>   inst->operands[1].type = AARCH64_OPND_HALF;
>   is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
>   if (! aarch64_wide_constant_p (value, is32, &shift_amount))
>     /* The constraint check should have guaranteed this wouldn't happen.  */
>-    assert (0);
>+    abort ();
>   value >>= shift_amount;
>   value &= 0xffff;
>   inst->operands[1].imm.value = value;
>diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
>index f9999adc28d..8a46f46dc2e 100644
>--- a/opcodes/aarch64-dis-2.c
>+++ b/opcodes/aarch64-dis-2.c
>@@ -24638,6 +24638,6 @@ aarch64_extract_operand (const aarch64_operand *self,
>       return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
>     case 220:
>       return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
>-    default: assert (0); abort ();
>+    default: abort ();
>     }
> }
>diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
>index 809cf8de930..be8fb3bd76a 100644
>--- a/opcodes/aarch64-dis.c
>+++ b/opcodes/aarch64-dis.c
>@@ -754,7 +754,7 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
> 	case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break;	/* per word */
> 	case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break;	/* per half */
> 	case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break;	/* per byte */
>-	default: assert (0); return false;
>+	default: return false;
> 	}
>       /* 00: 0; 01: 8; 10:16; 11:24.  */
>       info->shifter.amount = extract_field_2 (&field, code, 0) << 3;
>@@ -766,7 +766,6 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
>       info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8;
>       break;
>     default:
>-      assert (0);
>       return false;
>     }
> 
>@@ -908,7 +907,7 @@ decode_limm (uint32_t esize, aarch64_insn value, int64_t *result)
>     case 32: imm = (imm << 32) | imm;
>       /* Fall through.  */
>     case 64: break;
>-    default: assert (0); return 0;
>+    default: return 0;
>     }
> 
>   *result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4));
>@@ -1276,7 +1275,7 @@ aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
> 	    aarch64_sys_regs_sr[].  */
> 	value = value & ~(0x7);
> 	break;
>-    default: assert (0); return false;
>+    default: return false;
>     }
> 
>   for (i = 0; sysins_ops[i].name != NULL; ++i)
>@@ -1813,7 +1812,7 @@ aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self,
>       info->za_tile_vector.index.imm = 0;
>       break;
>     default:
>-      assert (0);
>+      abort ();
>     }
> 
>   return true;
>@@ -1885,7 +1884,7 @@ aarch64_ext_sme_sm_za (const aarch64_operand *self,
>   else if (fld_crm == 0x2)
>     info->reg.regno = 'z';
>   else
>-    assert (0);
>+    abort ();
> 
>   return true;
> }
>@@ -2204,7 +2203,6 @@ decode_asimd_fcvt (aarch64_inst *inst)
>       inst->operands[0].qualifier = qualifier;
>       break;
>     default:
>-      assert (0);
>       return 0;
>     }
> 
>@@ -3411,7 +3409,7 @@ print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst,
>     case ERR_UND:
>     case ERR_UNP:
>     case ERR_NYI:
>-      assert (0);
>+      abort ();
>     case ERR_VFI:
>       print_verifier_notes (mismatch_details, info);
>       break;
>diff --git a/opcodes/aarch64-gen.c b/opcodes/aarch64-gen.c
>index d0581bcf6e1..918b0688858 100644
>--- a/opcodes/aarch64-gen.c
>+++ b/opcodes/aarch64-gen.c
>@@ -1023,7 +1023,7 @@ print_operand_inserter (void)
> 	}
>     }
> 
>-  printf ("    default: assert (0); abort ();\n");
>+  printf ("    default: abort ();\n");
>   printf ("    }\n");
>   printf ("}\n");
> }
>@@ -1080,7 +1080,7 @@ print_operand_extractor (void)
> 	}
>     }
> 
>-  printf ("    default: assert (0); abort ();\n");
>+  printf ("    default: abort ();\n");
>   printf ("    }\n");
>   printf ("}\n");
> }
>@@ -1116,7 +1116,6 @@ print_get_opcode (void)
> 		       opcode->op,
> 		       aarch64_opcode_table[op_enum_table[opcode->op]].name,
> 		       opcode->name);
>-	      assert (0);
> 	      abort ();
> 	    }
> 	  assert (opcode->op < OP_TOTAL_NUM);
>diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
>index a37b3ffdd6d..4e212f92944 100644
>--- a/opcodes/aarch64-opc.c
>+++ b/opcodes/aarch64-opc.c
>@@ -2164,7 +2164,6 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
> 		    }
> 		  break;
> 		default:
>-		  assert (0);
> 		  return 0;
> 		}
> 	    }
>@@ -2349,7 +2348,6 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
> 		}
> 	      break;
> 	    default:
>-	      assert (0);
> 	      return 0;
> 	    }
> 	  /* Is the immediate valid?  */
>@@ -3048,7 +3046,7 @@ expand_fp_imm (int size, uint32_t imm8)
>   else
>     {
>       /* An unsupported size.  */
>-      assert (0);
>+      abort ();
>     }
> 
>   return imm;
>@@ -3595,7 +3593,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
> 	  snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
> 		    opnd->imm.value, opnd->imm.value);
> 	  break;
>-	default: assert (0);
>+	default: abort ();
> 	}
>       break;
> 
>@@ -3662,7 +3660,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
> 	      snprintf (buf, size,  "#%.18e", c.d);
> 	    }
> 	  break;
>-	default: assert (0);
>+	default: abort ();
> 	}
>       break;
> 
>@@ -3934,7 +3932,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
>       break;
> 
>     default:
>-      assert (0);
>+      abort ();
>     }
> }
> 
>diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
>index 49f3013c132..c6a4c7ba3cc 100644
>--- a/opcodes/aarch64-opc.h
>+++ b/opcodes/aarch64-opc.h
>@@ -465,7 +465,7 @@ select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
>     /* e.g. float2fix.  */
>     idx = 1;
>   else
>-    { assert (0); abort (); }
>+    abort ();
>   return idx;
> }
> 
>@@ -486,7 +486,7 @@ select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
>     /* e.g. float2fix.  */
>     idx = 0;
>   else
>-    { assert (0); abort (); }
>+    abort ();
>   return idx;
> }
> 
>@@ -506,7 +506,7 @@ select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
>       == AARCH64_OPND_CLASS_SISD_REG)
>     src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
>   if (src_size == dst_size && src_size == 0)
>-    { assert (0); abort (); }
>+    abort ();
>   /* When the result is not a sisd register or it is a long operantion.  */
>   if (dst_size == 0 || dst_size == src_size << 1)
>     return 1;
>@@ -549,10 +549,7 @@ get_logsz (unsigned int size)
>   const unsigned char ls[16] =
>     {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
>   if (size > 16)
>-    {
>-      assert (0);
>       return -1;
>-    }
>   assert (ls[size - 1] != (unsigned char)-1);
>   return ls[size - 1];
> }
>diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
>index 1888d9af488..6b5024e661f 100644
>--- a/opcodes/arm-dis.c
>+++ b/opcodes/arm-dis.c
>@@ -9856,7 +9856,7 @@ print_insn_mve (struct disassemble_info *info, long given)
> 				    print_mve_undefined (info, UNDEF_SIZE_0);
> 				    break;
> 				  default:
>-				    assert (0);
>+				    abort ();
> 				    break;
> 				  }
> 			      }

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Attachments on bug 28614: 13802