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(-)a/opcodes/aarch64-asm-2.c (-1 / +1 lines)
Lines 893-898 aarch64_insert_operand (const aarch64_operand *self, Link Here
893
      return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
893
      return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
894
    case 220:
894
    case 220:
895
      return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
895
      return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
896
    default: assert (0); abort ();
896
    default: abort ();
897
    }
897
    }
898
}
898
}
(-)a/opcodes/aarch64-asm.c (-13 / +13 lines)
Lines 147-153 aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, Link Here
147
	  insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);
147
	  insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);
148
	  break;
148
	  break;
149
	default:
149
	default:
150
	  assert (0);
150
	  abort ();
151
	}
151
	}
152
    }
152
    }
153
  else if (inst->opcode->iclass == cryptosm3)
153
  else if (inst->opcode->iclass == cryptosm3)
Lines 185-191 aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, Link Here
185
	  insert_field (FLD_H, code, reglane_index, 0);
185
	  insert_field (FLD_H, code, reglane_index, 0);
186
	  break;
186
	  break;
187
	default:
187
	default:
188
	  assert (0);
188
	  abort ();
189
	}
189
	}
190
    }
190
    }
191
  return true;
191
  return true;
Lines 229-235 aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED, Link Here
229
	case 2: value = 0xa; break;
229
	case 2: value = 0xa; break;
230
	case 3: value = 0x6; break;
230
	case 3: value = 0x6; break;
231
	case 4: value = 0x2; break;
231
	case 4: value = 0x2; break;
232
	default: assert (0);
232
	default: abort ();
233
	}
233
	}
234
      break;
234
      break;
235
    case 2:
235
    case 2:
Lines 242-248 aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED, Link Here
242
      value = 0x0;
242
      value = 0x0;
243
      break;
243
      break;
244
    default:
244
    default:
245
      assert (0);
245
      abort ();
246
    }
246
    }
247
  insert_field (FLD_opcode, code, value, 0);
247
  insert_field (FLD_opcode, code, value, 0);
248
248
Lines 315-321 aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, Link Here
315
      opcodeh2 = 0x2;
315
      opcodeh2 = 0x2;
316
      break;
316
      break;
317
    default:
317
    default:
318
      assert (0);
318
      abort ();
319
    }
319
    }
320
  insert_fields (code, QSsize, 0, 3, FLD_vldst_size, FLD_S, FLD_Q);
320
  insert_fields (code, QSsize, 0, 3, FLD_vldst_size, FLD_S, FLD_Q);
321
  gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
321
  gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
Lines 605-611 aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info, Link Here
605
	case AARCH64_OPND_QLF_S_S: value = 0; break;
605
	case AARCH64_OPND_QLF_S_S: value = 0; break;
606
	case AARCH64_OPND_QLF_S_D: value = 1; break;
606
	case AARCH64_OPND_QLF_S_D: value = 1; break;
607
	case AARCH64_OPND_QLF_S_Q: value = 2; break;
607
	case AARCH64_OPND_QLF_S_Q: value = 2; break;
608
	default: assert (0);
608
	default: abort ();
609
	}
609
	}
610
      insert_field (FLD_ldst_size, code, value, 0);
610
      insert_field (FLD_ldst_size, code, value, 0);
611
    }
611
    }
Lines 1372-1378 aarch64_ins_sme_za_hv_tiles (const aarch64_operand *self, Link Here
1372
      fld_zan_imm = regno;
1372
      fld_zan_imm = regno;
1373
      break;
1373
      break;
1374
    default:
1374
    default:
1375
      assert (0);
1375
      abort ();
1376
    }
1376
    }
1377
1377
1378
  insert_field (self->fields[0], code, fld_size, 0);
1378
  insert_field (self->fields[0], code, fld_size, 0);
Lines 1446-1452 aarch64_ins_sme_sm_za (const aarch64_operand *self, Link Here
1446
  else if (info->reg.regno == 'z')
1446
  else if (info->reg.regno == 'z')
1447
    fld_crm = 0x04; /* SVCRZA.  */
1447
    fld_crm = 0x04; /* SVCRZA.  */
1448
  else
1448
  else
1449
    assert (0);
1449
    abort ();
1450
1450
1451
  insert_field (self->fields[0], code, fld_crm, 0);
1451
  insert_field (self->fields[0], code, fld_crm, 0);
1452
  return true;
1452
  return true;
Lines 1510-1516 aarch64_ins_sme_pred_reg_with_index (const aarch64_operand *self, Link Here
1510
      fld_tshl = 0x0;
1510
      fld_tshl = 0x0;
1511
      break;
1511
      break;
1512
    default:
1512
    default:
1513
      assert (0);
1513
      abort ();
1514
  }
1514
  }
1515
1515
1516
  insert_field (self->fields[2], code, fld_i1, 0);
1516
  insert_field (self->fields[2], code, fld_i1, 0);
Lines 1544-1550 encode_asimd_fcvt (aarch64_inst *inst) Link Here
1544
      qualifier = inst->operands[0].qualifier;
1544
      qualifier = inst->operands[0].qualifier;
1545
      break;
1545
      break;
1546
    default:
1546
    default:
1547
      assert (0);
1547
      abort ();
1548
    }
1548
    }
1549
  assert (qualifier == AARCH64_OPND_QLF_V_4S
1549
  assert (qualifier == AARCH64_OPND_QLF_V_4S
1550
	  || qualifier == AARCH64_OPND_QLF_V_2D);
1550
	  || qualifier == AARCH64_OPND_QLF_V_2D);
Lines 1749-1755 do_special_encoding (struct aarch64_inst *inst) Link Here
1749
	case AARCH64_OPND_QLF_S_S: value = 0; break;
1749
	case AARCH64_OPND_QLF_S_S: value = 0; break;
1750
	case AARCH64_OPND_QLF_S_D: value = 1; break;
1750
	case AARCH64_OPND_QLF_S_D: value = 1; break;
1751
	case AARCH64_OPND_QLF_S_H: value = 3; break;
1751
	case AARCH64_OPND_QLF_S_H: value = 3; break;
1752
	default: assert (0);
1752
	default: abort ();
1753
	}
1753
	}
1754
      insert_field (FLD_type, &inst->value, value, 0);
1754
      insert_field (FLD_type, &inst->value, value, 0);
1755
    }
1755
    }
Lines 2098-2110 convert_mov_to_movewide (aarch64_inst *inst) Link Here
2098
      value = ~inst->operands[1].imm.value;
2098
      value = ~inst->operands[1].imm.value;
2099
      break;
2099
      break;
2100
    default:
2100
    default:
2101
      assert (0);
2101
      abort ();
2102
    }
2102
    }
2103
  inst->operands[1].type = AARCH64_OPND_HALF;
2103
  inst->operands[1].type = AARCH64_OPND_HALF;
2104
  is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
2104
  is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
2105
  if (! aarch64_wide_constant_p (value, is32, &shift_amount))
2105
  if (! aarch64_wide_constant_p (value, is32, &shift_amount))
2106
    /* The constraint check should have guaranteed this wouldn't happen.  */
2106
    /* The constraint check should have guaranteed this wouldn't happen.  */
2107
    assert (0);
2107
    abort ();
2108
  value >>= shift_amount;
2108
  value >>= shift_amount;
2109
  value &= 0xffff;
2109
  value &= 0xffff;
2110
  inst->operands[1].imm.value = value;
2110
  inst->operands[1].imm.value = value;
(-)a/opcodes/aarch64-dis-2.c (-1 / +1 lines)
Lines 24638-24643 aarch64_extract_operand (const aarch64_operand *self, Link Here
24638
      return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
24638
      return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
24639
    case 220:
24639
    case 220:
24640
      return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
24640
      return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
24641
    default: assert (0); abort ();
24641
    default: abort ();
24642
    }
24642
    }
24643
}
24643
}
(-)a/opcodes/aarch64-dis.c (-8 / +6 lines)
Lines 754-760 aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, Link Here
754
	case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break;	/* per word */
754
	case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break;	/* per word */
755
	case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break;	/* per half */
755
	case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break;	/* per half */
756
	case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break;	/* per byte */
756
	case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break;	/* per byte */
757
	default: assert (0); return false;
757
	default: return false;
758
	}
758
	}
759
      /* 00: 0; 01: 8; 10:16; 11:24.  */
759
      /* 00: 0; 01: 8; 10:16; 11:24.  */
760
      info->shifter.amount = extract_field_2 (&field, code, 0) << 3;
760
      info->shifter.amount = extract_field_2 (&field, code, 0) << 3;
Lines 766-772 aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, Link Here
766
      info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8;
766
      info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8;
767
      break;
767
      break;
768
    default:
768
    default:
769
      assert (0);
770
      return false;
769
      return false;
771
    }
770
    }
772
771
Lines 908-914 decode_limm (uint32_t esize, aarch64_insn value, int64_t *result) Link Here
908
    case 32: imm = (imm << 32) | imm;
907
    case 32: imm = (imm << 32) | imm;
909
      /* Fall through.  */
908
      /* Fall through.  */
910
    case 64: break;
909
    case 64: break;
911
    default: assert (0); return 0;
910
    default: return 0;
912
    }
911
    }
913
912
914
  *result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4));
913
  *result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4));
Lines 1276-1282 aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, Link Here
1276
	    aarch64_sys_regs_sr[].  */
1275
	    aarch64_sys_regs_sr[].  */
1277
	value = value & ~(0x7);
1276
	value = value & ~(0x7);
1278
	break;
1277
	break;
1279
    default: assert (0); return false;
1278
    default: return false;
1280
    }
1279
    }
1281
1280
1282
  for (i = 0; sysins_ops[i].name != NULL; ++i)
1281
  for (i = 0; sysins_ops[i].name != NULL; ++i)
Lines 1813-1819 aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self, Link Here
1813
      info->za_tile_vector.index.imm = 0;
1812
      info->za_tile_vector.index.imm = 0;
1814
      break;
1813
      break;
1815
    default:
1814
    default:
1816
      assert (0);
1815
      abort ();
1817
    }
1816
    }
1818
1817
1819
  return true;
1818
  return true;
Lines 1885-1891 aarch64_ext_sme_sm_za (const aarch64_operand *self, Link Here
1885
  else if (fld_crm == 0x2)
1884
  else if (fld_crm == 0x2)
1886
    info->reg.regno = 'z';
1885
    info->reg.regno = 'z';
1887
  else
1886
  else
1888
    assert (0);
1887
    abort ();
1889
1888
1890
  return true;
1889
  return true;
1891
}
1890
}
Lines 2204-2210 decode_asimd_fcvt (aarch64_inst *inst) Link Here
2204
      inst->operands[0].qualifier = qualifier;
2203
      inst->operands[0].qualifier = qualifier;
2205
      break;
2204
      break;
2206
    default:
2205
    default:
2207
      assert (0);
2208
      return 0;
2206
      return 0;
2209
    }
2207
    }
2210
2208
Lines 3411-3417 print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst, Link Here
3411
    case ERR_UND:
3409
    case ERR_UND:
3412
    case ERR_UNP:
3410
    case ERR_UNP:
3413
    case ERR_NYI:
3411
    case ERR_NYI:
3414
      assert (0);
3412
      abort ();
3415
    case ERR_VFI:
3413
    case ERR_VFI:
3416
      print_verifier_notes (mismatch_details, info);
3414
      print_verifier_notes (mismatch_details, info);
3417
      break;
3415
      break;
(-)a/opcodes/aarch64-gen.c (-3 / +2 lines)
Lines 1023-1029 print_operand_inserter (void) Link Here
1023
	}
1023
	}
1024
    }
1024
    }
1025
1025
1026
  printf ("    default: assert (0); abort ();\n");
1026
  printf ("    default: abort ();\n");
1027
  printf ("    }\n");
1027
  printf ("    }\n");
1028
  printf ("}\n");
1028
  printf ("}\n");
1029
}
1029
}
Lines 1080-1086 print_operand_extractor (void) Link Here
1080
	}
1080
	}
1081
    }
1081
    }
1082
1082
1083
  printf ("    default: assert (0); abort ();\n");
1083
  printf ("    default: abort ();\n");
1084
  printf ("    }\n");
1084
  printf ("    }\n");
1085
  printf ("}\n");
1085
  printf ("}\n");
1086
}
1086
}
Lines 1116-1122 print_get_opcode (void) Link Here
1116
		       opcode->op,
1116
		       opcode->op,
1117
		       aarch64_opcode_table[op_enum_table[opcode->op]].name,
1117
		       aarch64_opcode_table[op_enum_table[opcode->op]].name,
1118
		       opcode->name);
1118
		       opcode->name);
1119
	      assert (0);
1120
	      abort ();
1119
	      abort ();
1121
	    }
1120
	    }
1122
	  assert (opcode->op < OP_TOTAL_NUM);
1121
	  assert (opcode->op < OP_TOTAL_NUM);
(-)a/opcodes/aarch64-opc.c (-6 / +4 lines)
Lines 2164-2170 operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, Link Here
2164
		    }
2164
		    }
2165
		  break;
2165
		  break;
2166
		default:
2166
		default:
2167
		  assert (0);
2168
		  return 0;
2167
		  return 0;
2169
		}
2168
		}
2170
	    }
2169
	    }
Lines 2349-2355 operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, Link Here
2349
		}
2348
		}
2350
	      break;
2349
	      break;
2351
	    default:
2350
	    default:
2352
	      assert (0);
2353
	      return 0;
2351
	      return 0;
2354
	    }
2352
	    }
2355
	  /* Is the immediate valid?  */
2353
	  /* Is the immediate valid?  */
Lines 3048-3054 expand_fp_imm (int size, uint32_t imm8) Link Here
3048
  else
3046
  else
3049
    {
3047
    {
3050
      /* An unsupported size.  */
3048
      /* An unsupported size.  */
3051
      assert (0);
3049
      abort ();
3052
    }
3050
    }
3053
3051
3054
  return imm;
3052
  return imm;
Lines 3595-3601 aarch64_print_operand (char *buf, size_t size, bfd_vma pc, Link Here
3595
	  snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
3593
	  snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
3596
		    opnd->imm.value, opnd->imm.value);
3594
		    opnd->imm.value, opnd->imm.value);
3597
	  break;
3595
	  break;
3598
	default: assert (0);
3596
	default: abort ();
3599
	}
3597
	}
3600
      break;
3598
      break;
3601
3599
Lines 3662-3668 aarch64_print_operand (char *buf, size_t size, bfd_vma pc, Link Here
3662
	      snprintf (buf, size,  "#%.18e", c.d);
3660
	      snprintf (buf, size,  "#%.18e", c.d);
3663
	    }
3661
	    }
3664
	  break;
3662
	  break;
3665
	default: assert (0);
3663
	default: abort ();
3666
	}
3664
	}
3667
      break;
3665
      break;
3668
3666
Lines 3934-3940 aarch64_print_operand (char *buf, size_t size, bfd_vma pc, Link Here
3934
      break;
3932
      break;
3935
3933
3936
    default:
3934
    default:
3937
      assert (0);
3935
      abort ();
3938
    }
3936
    }
3939
}
3937
}
3940
3938
(-)a/opcodes/aarch64-opc.h (-6 / +3 lines)
Lines 465-471 select_operand_for_sf_field_coding (const aarch64_opcode *opcode) Link Here
465
    /* e.g. float2fix.  */
465
    /* e.g. float2fix.  */
466
    idx = 1;
466
    idx = 1;
467
  else
467
  else
468
    { assert (0); abort (); }
468
    abort ();
469
  return idx;
469
  return idx;
470
}
470
}
471
471
Lines 486-492 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode) Link Here
486
    /* e.g. float2fix.  */
486
    /* e.g. float2fix.  */
487
    idx = 0;
487
    idx = 0;
488
  else
488
  else
489
    { assert (0); abort (); }
489
    abort ();
490
  return idx;
490
  return idx;
491
}
491
}
492
492
Lines 506-512 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode) Link Here
506
      == AARCH64_OPND_CLASS_SISD_REG)
506
      == AARCH64_OPND_CLASS_SISD_REG)
507
    src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
507
    src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
508
  if (src_size == dst_size && src_size == 0)
508
  if (src_size == dst_size && src_size == 0)
509
    { assert (0); abort (); }
509
    abort ();
510
  /* When the result is not a sisd register or it is a long operantion.  */
510
  /* When the result is not a sisd register or it is a long operantion.  */
511
  if (dst_size == 0 || dst_size == src_size << 1)
511
  if (dst_size == 0 || dst_size == src_size << 1)
512
    return 1;
512
    return 1;
Lines 549-558 get_logsz (unsigned int size) Link Here
549
  const unsigned char ls[16] =
549
  const unsigned char ls[16] =
550
    {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
550
    {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
551
  if (size > 16)
551
  if (size > 16)
552
    {
553
      assert (0);
554
      return -1;
552
      return -1;
555
    }
556
  assert (ls[size - 1] != (unsigned char)-1);
553
  assert (ls[size - 1] != (unsigned char)-1);
557
  return ls[size - 1];
554
  return ls[size - 1];
558
}
555
}
(-)a/opcodes/arm-dis.c (-1 / +1 lines)
Lines 9856-9862 print_insn_mve (struct disassemble_info *info, long given) Link Here
9856
				    print_mve_undefined (info, UNDEF_SIZE_0);
9856
				    print_mve_undefined (info, UNDEF_SIZE_0);
9857
				    break;
9857
				    break;
9858
				  default:
9858
				  default:
9859
				    assert (0);
9859
				    abort ();
9860
				    break;
9860
				    break;
9861
				  }
9861
				  }
9862
			      }
9862
			      }

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