Attachment 12249 Details for Bug 25469 – Add support GBZ80, Z80N CPUs and DWARF

[patch] Add support GBZ80, Z80N CPUs and DWARF

gbz80-z80n-support.patch (text/plain), 177.88 KB, created by Sergey Belyashov on 2020-02-04 10:00:53 UTC

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Creator: Sergey Belyashov

Created: 2020-02-04 10:00:53 UTC

Size: 177.88 KB

patch

obsolete

>From b5116f56196c7983f65a0b642976519d71ba2ce1 Mon Sep 17 00:00:00 2001
>From: Sergey Belyashov <Sergey.Belyashov@gmail.com>
>Date: Mon, 27 Jan 2020 15:25:58 +0300
>Subject: [PATCH 1/7] [Z80] Add support for GameBoy Z80 CPU
>
>---
> bfd/bfd-in2.h                     |   2 +-
> gas/config/tc-z80.c               |  64 +++-
> gas/doc/c-z80.texi                |   4 +
> gas/testsuite/gas/z80/gbz80_all.d | 509 +++++++++++++++++++++++++++++
> gas/testsuite/gas/z80/gbz80_all.s | 515 ++++++++++++++++++++++++++++++
> gas/testsuite/gas/z80/z80.exp     |   2 +
> opcodes/z80-dis.c                 | 101 +++++-
> 7 files changed, 1179 insertions(+), 18 deletions(-)
> create mode 100644 gas/testsuite/gas/z80/gbz80_all.d
> create mode 100644 gas/testsuite/gas/z80/gbz80_all.s
>
>diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
>index 7c13bc8c91..b9143d3593 100644
>--- a/bfd/bfd-in2.h
>+++ b/bfd/bfd-in2.h
>@@ -1888,13 +1888,13 @@ enum bfd_architecture
>   bfd_arch_xtensa,    /* Tensilica's Xtensa cores.  */
> #define bfd_mach_xtensa        1
>   bfd_arch_z80,
>-#define bfd_mach_gbz80         0 /* GameBoy Z80 (reduced instruction set) */
> #define bfd_mach_z80strict     1 /* Z80 without undocumented opcodes.  */
> #define bfd_mach_z180          2 /* Z180: successor with additional instructions, but without halves of ix and iy */
> #define bfd_mach_z80           3 /* Z80 with ixl, ixh, iyl, and iyh.  */
> #define bfd_mach_ez80_z80      4 /* eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode */
> #define bfd_mach_ez80_adl      5 /* eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode */
> #define bfd_mach_z80full       7 /* Z80 with all undocumented instructions.  */
>+#define bfd_mach_gbz80         8 /* GameBoy Z80 (reduced instruction set) */
> #define bfd_mach_r800          11 /* R800: successor with multiplication.  */
>   bfd_arch_lm32,      /* Lattice Mico32.  */
> #define bfd_mach_lm32          1
>diff --git a/gas/config/tc-z80.c b/gas/config/tc-z80.c
>index d823549ff0..468e21f7b3 100644
>--- a/gas/config/tc-z80.c
>+++ b/gas/config/tc-z80.c
>@@ -85,6 +85,7 @@ struct option md_longopts[] =
>   { "z180",      no_argument, NULL, OPTION_MACH_Z180},
>   { "ez80",      no_argument, NULL, OPTION_MACH_EZ80_Z80},
>   { "ez80-adl",  no_argument, NULL, OPTION_MACH_EZ80_ADL},
>+  { "gbz80",     no_argument, NULL, OPTION_MACH_GBZ80},
>   { "fp-s",      required_argument, NULL, OPTION_FP_SINGLE_FORMAT},
>   { "fp-d",      required_argument, NULL, OPTION_FP_DOUBLE_FORMAT},
>   { "strict",    no_argument, NULL, OPTION_MACH_FUD},
>@@ -330,6 +331,7 @@ CPU model options:\n\
>   -z180\t\t\t  assemble for Z180\n\
>   -ez80\t\t\t  assemble for eZ80 in Z80 mode by default\n\
>   -ez80-adl\t\t  assemble for eZ80 in ADL mode by default\n\
>+  -gbz80\t\t  assemble for GameBoy Z80\n\
> \n\
> Compatibility options:\n\
>   -local-prefix=TEXT\t  treat labels prefixed by TEXT as local\n\
>@@ -1339,6 +1341,25 @@ emit_s (char prefix, char opcode, const char *args)
>   return p;
> }
> 
>+static const char *
>+emit_sub (char prefix, char opcode, const char *args)
>+{
>+  expressionS arg_s;
>+  const char *p;
>+
>+  if (!(ins_ok & INS_GBZ80))
>+    return emit_s (prefix, opcode, args);
>+  p = parse_exp (args, & arg_s);
>+  if (*p != ',' || arg_s.X_md != 0 || arg_s.X_op != O_register || arg_s.X_add_number != REG_A)
>+    ill_op ();
>+
>+  ++p;
>+  p = parse_exp (p, & arg_s);
>+
>+  emit_sx (prefix, opcode, & arg_s);
>+  return p;
>+}
>+
> static const char *
> emit_call (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
> {
>@@ -1576,6 +1597,14 @@ emit_add (char prefix, char opcode, const char * args)
>       case REG_A:
> 	p = emit_s (0, prefix, p);
> 	break;
>+      case REG_SP:
>+	p = parse_exp (p, &term);
>+	if (!(ins_ok & INS_GBZ80) || term.X_md || term.X_op == O_register)
>+	  ill_op ();
>+	q = frag_more (1);
>+	*q = 0xE8;
>+	emit_byte (&term, BFD_RELOC_Z80_DISP8);
>+	break;
>       case REG_HL:
> 	lhs = term.X_add_number;
> 	p = parse_exp (p, &term);
>@@ -1998,7 +2027,7 @@ emit_ld_m_r (expressionS *dst, expressionS *src)
>       if (src->X_add_number == REG_A)
>         {
>           q = frag_more (1);
>-          *q = 0x32;
>+	  *q = (ins_ok & INS_GBZ80) ? 0xEA : 0x32;
>           emit_word (dst);
>           return;
>         }
>@@ -2140,7 +2169,7 @@ emit_ld_r_m (expressionS *dst, expressionS *src)
>       if (dst->X_add_number == REG_A)
>         {
>           q = frag_more (1);
>-          *q = 0x3A;
>+	  *q = (ins_ok & INS_GBZ80) ? 0xFA : 0x3A;
>           emit_word (src);
>         }
>     }
>@@ -2208,8 +2237,6 @@ emit_ld_r_r (expressionS *dst, expressionS *src)
>         default:
>           ill_op ();
>         }
>-      if (ins_ok & INS_GBZ80)
>-        ill_op ();
>       opcode = 0xF9;
>       break;
>     case REG_HL:
>@@ -2522,7 +2549,7 @@ emit_lddldi (char prefix, char opcode, const char * args)
>   p = parse_exp (args, & dst);
>   if (*p++ != ',')
>     error (_("bad instruction syntax"));
>-  p = parse_exp (args, & src);
>+  p = parse_exp (p, & src);
> 
>   if (dst.X_op != O_register || src.X_op != O_register)
>     ill_op ();
>@@ -2604,6 +2631,29 @@ emit_ldh (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED,
>   return p;
> }
> 
>+static const char *
>+emit_ldhl (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
>+{
>+  expressionS dst, src;
>+  const char *p;
>+  char *q;
>+  p = parse_exp (args, & dst);
>+  if (*p++ != ',')
>+    {
>+      error (_("bad instruction syntax"));
>+      return p;
>+    }
>+
>+  p = parse_exp (p, & src);
>+  if (dst.X_md || dst.X_op != O_register || dst.X_add_number != REG_SP
>+      || src.X_md || src.X_op == O_register || src.X_op == O_md1)
>+    ill_op ();
>+  q = frag_more (1);
>+  *q = opcode;
>+  emit_byte (& src, BFD_RELOC_Z80_DISP8);
>+  return p;
>+}
>+
> static const char *
> parse_lea_pea_args (const char * args, expressionS *op)
> {
>@@ -3192,7 +3242,7 @@ static table_t instab[] =
>   { "ldd",  0xED, 0xA8, emit_lddldi,INS_ALL }, /* GBZ80 has special meaning */
>   { "lddr", 0xED, 0xB8, emit_insn, INS_NOT_GBZ80 },
>   { "ldh",  0xE0, 0x00, emit_ldh,  INS_GBZ80 },
>-  { "ldhl", 0xE0, 0x00, emit_ldh,  INS_GBZ80 },
>+  { "ldhl", 0x00, 0xF8, emit_ldhl, INS_GBZ80 },
>   { "ldi",  0xED, 0xA0, emit_lddldi,INS_ALL }, /* GBZ80 has special meaning */
>   { "ldir", 0xED, 0xB0, emit_insn, INS_NOT_GBZ80 },
>   { "lea",  0xED, 0x02, emit_lea,  INS_EZ80 },
>@@ -3248,7 +3298,7 @@ static table_t instab[] =
>   { "srl",  0xCB, 0x38, emit_mr,   INS_ALL },
>   { "stmix",0xED, 0x7D, emit_insn, INS_EZ80 },
>   { "stop", 0x00, 0x10, emit_insn, INS_GBZ80 },
>-  { "sub",  0x00, 0x90, emit_s,    INS_ALL },
>+  { "sub",  0x00, 0x90, emit_sub,  INS_ALL },
>   { "swap", 0xCB, 0x30, emit_mr,   INS_GBZ80 },
>   { "tst",  0xED, 0x04, emit_tst,  INS_Z180|INS_EZ80 },
>   { "tstio",0xED, 0x74, emit_tstio,INS_Z180|INS_EZ80 },
>diff --git a/gas/doc/c-z80.texi b/gas/doc/c-z80.texi
>index dd6332d670..d6b4d3f443 100644
>--- a/gas/doc/c-z80.texi
>+++ b/gas/doc/c-z80.texi
>@@ -53,6 +53,10 @@ Produce code for the eZ80 processor in Z80 memory mode by default.
> @item -ez80-adl
> Produce code for the eZ80 processor in ADL memory mode by default.
> 
>+@cindex @code{-gbz80} command-line option, Z80
>+@item -gbz80
>+Produce code for the GameBoy Z80 processor.
>+
> @cindex @code{-local-prefix} command-line option, Z80
> @item  -local-prefix=@var{prefix}
> Mark all labels with specified prefix as local. But such label can be
>diff --git a/gas/testsuite/gas/z80/gbz80_all.d b/gas/testsuite/gas/z80/gbz80_all.d
>new file mode 100644
>index 0000000000..bac007fc3a
>--- /dev/null
>+++ b/gas/testsuite/gas/z80/gbz80_all.d
>@@ -0,0 +1,509 @@
>+#as: -gbz80
>+#objdump: -d
>+#name: GBZ80 instruction set
>+
>+.*: .*
>+
>+Disassembly of section .text:
>+
>+0+ <.text>:
>+\s+[0-9a-f]+:\s+00\s+nop
>+\s+[0-9a-f]+:\s+01 af be\s+ld bc,0xbeaf
>+\s+[0-9a-f]+:\s+02\s+ld $bc$,a
>+\s+[0-9a-f]+:\s+03\s+inc bc
>+\s+[0-9a-f]+:\s+04\s+inc b
>+\s+[0-9a-f]+:\s+05\s+dec b
>+\s+[0-9a-f]+:\s+06 fd\s+ld b,0xfd
>+\s+[0-9a-f]+:\s+07\s+rlca
>+\s+[0-9a-f]+:\s+08 af be\s+ld $0xbeaf$,sp
>+\s+[0-9a-f]+:\s+09\s+add hl,bc
>+\s+[0-9a-f]+:\s+0a\s+ld a,$bc$
>+\s+[0-9a-f]+:\s+0b\s+dec bc
>+\s+[0-9a-f]+:\s+0c\s+inc c
>+\s+[0-9a-f]+:\s+0d\s+dec c
>+\s+[0-9a-f]+:\s+0e fd\s+ld c,0xfd
>+\s+[0-9a-f]+:\s+0f\s+rrca
>+\s+[0-9a-f]+:\s+10\s+stop
>+\s+[0-9a-f]+:\s+11 af be\s+ld de,0xbeaf
>+\s+[0-9a-f]+:\s+12\s+ld $de$,a
>+\s+[0-9a-f]+:\s+13\s+inc de
>+\s+[0-9a-f]+:\s+14\s+inc d
>+\s+[0-9a-f]+:\s+15\s+dec d
>+\s+[0-9a-f]+:\s+16 fd\s+ld d,0xfd
>+\s+[0-9a-f]+:\s+17\s+rla
>+\s+[0-9a-f]+:\s+18 0a\s+jr 0x002d
>+\s+[0-9a-f]+:\s+19\s+add hl,de
>+\s+[0-9a-f]+:\s+1a\s+ld a,$de$
>+\s+[0-9a-f]+:\s+1b\s+dec de
>+\s+[0-9a-f]+:\s+1c\s+inc e
>+\s+[0-9a-f]+:\s+1d\s+dec e
>+\s+[0-9a-f]+:\s+1e fd\s+ld e,0xfd
>+\s+[0-9a-f]+:\s+1f\s+rra
>+\s+[0-9a-f]+:\s+20 0a\s+jr nz,0x0037
>+\s+[0-9a-f]+:\s+21 af be\s+ld hl,0xbeaf
>+\s+[0-9a-f]+:\s+22\s+ldi $hl$,a
>+\s+[0-9a-f]+:\s+23\s+inc hl
>+\s+[0-9a-f]+:\s+24\s+inc h
>+\s+[0-9a-f]+:\s+25\s+dec h
>+\s+[0-9a-f]+:\s+26 fd\s+ld h,0xfd
>+\s+[0-9a-f]+:\s+27\s+daa
>+\s+[0-9a-f]+:\s+28 0a\s+jr z,0x0043
>+\s+[0-9a-f]+:\s+29\s+add hl,hl
>+\s+[0-9a-f]+:\s+2a\s+ldi a,$hl$
>+\s+[0-9a-f]+:\s+2b\s+dec hl
>+\s+[0-9a-f]+:\s+2c\s+inc l
>+\s+[0-9a-f]+:\s+2d\s+dec l
>+\s+[0-9a-f]+:\s+2e fd\s+ld l,0xfd
>+\s+[0-9a-f]+:\s+2f\s+cpl
>+\s+[0-9a-f]+:\s+30 0a\s+jr nc,0x004d
>+\s+[0-9a-f]+:\s+31 af be\s+ld sp,0xbeaf
>+\s+[0-9a-f]+:\s+32\s+ldd $hl$,a
>+\s+[0-9a-f]+:\s+33\s+inc sp
>+\s+[0-9a-f]+:\s+34\s+inc $hl$
>+\s+[0-9a-f]+:\s+35\s+dec $hl$
>+\s+[0-9a-f]+:\s+36 fd\s+ld $hl$,0xfd
>+\s+[0-9a-f]+:\s+37\s+scf
>+\s+[0-9a-f]+:\s+38 0a\s+jr c,0x0059
>+\s+[0-9a-f]+:\s+39\s+add hl,sp
>+\s+[0-9a-f]+:\s+3a\s+ldd a,$hl$
>+\s+[0-9a-f]+:\s+3b\s+dec sp
>+\s+[0-9a-f]+:\s+3c\s+inc a
>+\s+[0-9a-f]+:\s+3d\s+dec a
>+\s+[0-9a-f]+:\s+3e fd\s+ld a,0xfd
>+\s+[0-9a-f]+:\s+3f\s+ccf
>+\s+[0-9a-f]+:\s+40\s+ld b,b
>+\s+[0-9a-f]+:\s+41\s+ld b,c
>+\s+[0-9a-f]+:\s+42\s+ld b,d
>+\s+[0-9a-f]+:\s+43\s+ld b,e
>+\s+[0-9a-f]+:\s+44\s+ld b,h
>+\s+[0-9a-f]+:\s+45\s+ld b,l
>+\s+[0-9a-f]+:\s+46\s+ld b,$hl$
>+\s+[0-9a-f]+:\s+47\s+ld b,a
>+\s+[0-9a-f]+:\s+48\s+ld c,b
>+\s+[0-9a-f]+:\s+49\s+ld c,c
>+\s+[0-9a-f]+:\s+4a\s+ld c,d
>+\s+[0-9a-f]+:\s+4b\s+ld c,e
>+\s+[0-9a-f]+:\s+4c\s+ld c,h
>+\s+[0-9a-f]+:\s+4d\s+ld c,l
>+\s+[0-9a-f]+:\s+4e\s+ld c,$hl$
>+\s+[0-9a-f]+:\s+4f\s+ld c,a
>+\s+[0-9a-f]+:\s+50\s+ld d,b
>+\s+[0-9a-f]+:\s+51\s+ld d,c
>+\s+[0-9a-f]+:\s+52\s+ld d,d
>+\s+[0-9a-f]+:\s+53\s+ld d,e
>+\s+[0-9a-f]+:\s+54\s+ld d,h
>+\s+[0-9a-f]+:\s+55\s+ld d,l
>+\s+[0-9a-f]+:\s+56\s+ld d,$hl$
>+\s+[0-9a-f]+:\s+57\s+ld d,a
>+\s+[0-9a-f]+:\s+58\s+ld e,b
>+\s+[0-9a-f]+:\s+59\s+ld e,c
>+\s+[0-9a-f]+:\s+5a\s+ld e,d
>+\s+[0-9a-f]+:\s+5b\s+ld e,e
>+\s+[0-9a-f]+:\s+5c\s+ld e,h
>+\s+[0-9a-f]+:\s+5d\s+ld e,l
>+\s+[0-9a-f]+:\s+5e\s+ld e,$hl$
>+\s+[0-9a-f]+:\s+5f\s+ld e,a
>+\s+[0-9a-f]+:\s+60\s+ld h,b
>+\s+[0-9a-f]+:\s+61\s+ld h,c
>+\s+[0-9a-f]+:\s+62\s+ld h,d
>+\s+[0-9a-f]+:\s+63\s+ld h,e
>+\s+[0-9a-f]+:\s+64\s+ld h,h
>+\s+[0-9a-f]+:\s+65\s+ld h,l
>+\s+[0-9a-f]+:\s+66\s+ld h,$hl$
>+\s+[0-9a-f]+:\s+67\s+ld h,a
>+\s+[0-9a-f]+:\s+68\s+ld l,b
>+\s+[0-9a-f]+:\s+69\s+ld l,c
>+\s+[0-9a-f]+:\s+6a\s+ld l,d
>+\s+[0-9a-f]+:\s+6b\s+ld l,e
>+\s+[0-9a-f]+:\s+6c\s+ld l,h
>+\s+[0-9a-f]+:\s+6d\s+ld l,l
>+\s+[0-9a-f]+:\s+6e\s+ld l,$hl$
>+\s+[0-9a-f]+:\s+6f\s+ld l,a
>+\s+[0-9a-f]+:\s+70\s+ld $hl$,b
>+\s+[0-9a-f]+:\s+71\s+ld $hl$,c
>+\s+[0-9a-f]+:\s+72\s+ld $hl$,d
>+\s+[0-9a-f]+:\s+73\s+ld $hl$,e
>+\s+[0-9a-f]+:\s+74\s+ld $hl$,h
>+\s+[0-9a-f]+:\s+75\s+ld $hl$,l
>+\s+[0-9a-f]+:\s+76\s+halt
>+\s+[0-9a-f]+:\s+77\s+ld $hl$,a
>+\s+[0-9a-f]+:\s+78\s+ld a,b
>+\s+[0-9a-f]+:\s+79\s+ld a,c
>+\s+[0-9a-f]+:\s+7a\s+ld a,d
>+\s+[0-9a-f]+:\s+7b\s+ld a,e
>+\s+[0-9a-f]+:\s+7c\s+ld a,h
>+\s+[0-9a-f]+:\s+7d\s+ld a,l
>+\s+[0-9a-f]+:\s+7e\s+ld a,$hl$
>+\s+[0-9a-f]+:\s+7f\s+ld a,a
>+\s+[0-9a-f]+:\s+80\s+add a,b
>+\s+[0-9a-f]+:\s+81\s+add a,c
>+\s+[0-9a-f]+:\s+82\s+add a,d
>+\s+[0-9a-f]+:\s+83\s+add a,e
>+\s+[0-9a-f]+:\s+84\s+add a,h
>+\s+[0-9a-f]+:\s+85\s+add a,l
>+\s+[0-9a-f]+:\s+86\s+add a,$hl$
>+\s+[0-9a-f]+:\s+87\s+add a,a
>+\s+[0-9a-f]+:\s+88\s+adc a,b
>+\s+[0-9a-f]+:\s+89\s+adc a,c
>+\s+[0-9a-f]+:\s+8a\s+adc a,d
>+\s+[0-9a-f]+:\s+8b\s+adc a,e
>+\s+[0-9a-f]+:\s+8c\s+adc a,h
>+\s+[0-9a-f]+:\s+8d\s+adc a,l
>+\s+[0-9a-f]+:\s+8e\s+adc a,$hl$
>+\s+[0-9a-f]+:\s+8f\s+adc a,a
>+\s+[0-9a-f]+:\s+90\s+sub a,b
>+\s+[0-9a-f]+:\s+91\s+sub a,c
>+\s+[0-9a-f]+:\s+92\s+sub a,d
>+\s+[0-9a-f]+:\s+93\s+sub a,e
>+\s+[0-9a-f]+:\s+94\s+sub a,h
>+\s+[0-9a-f]+:\s+95\s+sub a,l
>+\s+[0-9a-f]+:\s+96\s+sub a,$hl$
>+\s+[0-9a-f]+:\s+97\s+sub a,a
>+\s+[0-9a-f]+:\s+98\s+sbc a,b
>+\s+[0-9a-f]+:\s+99\s+sbc a,c
>+\s+[0-9a-f]+:\s+9a\s+sbc a,d
>+\s+[0-9a-f]+:\s+9b\s+sbc a,e
>+\s+[0-9a-f]+:\s+9c\s+sbc a,h
>+\s+[0-9a-f]+:\s+9d\s+sbc a,l
>+\s+[0-9a-f]+:\s+9e\s+sbc a,$hl$
>+\s+[0-9a-f]+:\s+9f\s+sbc a,a
>+\s+[0-9a-f]+:\s+a0\s+and b
>+\s+[0-9a-f]+:\s+a1\s+and c
>+\s+[0-9a-f]+:\s+a2\s+and d
>+\s+[0-9a-f]+:\s+a3\s+and e
>+\s+[0-9a-f]+:\s+a4\s+and h
>+\s+[0-9a-f]+:\s+a5\s+and l
>+\s+[0-9a-f]+:\s+a6\s+and $hl$
>+\s+[0-9a-f]+:\s+a7\s+and a
>+\s+[0-9a-f]+:\s+a8\s+xor b
>+\s+[0-9a-f]+:\s+a9\s+xor c
>+\s+[0-9a-f]+:\s+aa\s+xor d
>+\s+[0-9a-f]+:\s+ab\s+xor e
>+\s+[0-9a-f]+:\s+ac\s+xor h
>+\s+[0-9a-f]+:\s+ad\s+xor l
>+\s+[0-9a-f]+:\s+ae\s+xor $hl$
>+\s+[0-9a-f]+:\s+af\s+xor a
>+\s+[0-9a-f]+:\s+b0\s+or b
>+\s+[0-9a-f]+:\s+b1\s+or c
>+\s+[0-9a-f]+:\s+b2\s+or d
>+\s+[0-9a-f]+:\s+b3\s+or e
>+\s+[0-9a-f]+:\s+b4\s+or h
>+\s+[0-9a-f]+:\s+b5\s+or l
>+\s+[0-9a-f]+:\s+b6\s+or $hl$
>+\s+[0-9a-f]+:\s+b7\s+or a
>+\s+[0-9a-f]+:\s+b8\s+cp b
>+\s+[0-9a-f]+:\s+b9\s+cp c
>+\s+[0-9a-f]+:\s+ba\s+cp d
>+\s+[0-9a-f]+:\s+bb\s+cp e
>+\s+[0-9a-f]+:\s+bc\s+cp h
>+\s+[0-9a-f]+:\s+bd\s+cp l
>+\s+[0-9a-f]+:\s+be\s+cp $hl$
>+\s+[0-9a-f]+:\s+bf\s+cp a
>+\s+[0-9a-f]+:\s+c0\s+ret nz
>+\s+[0-9a-f]+:\s+c1\s+pop bc
>+\s+[0-9a-f]+:\s+c2 af be\s+jp nz,0xbeaf
>+\s+[0-9a-f]+:\s+c3 af be\s+jp 0xbeaf
>+\s+[0-9a-f]+:\s+c4 af be\s+call nz,0xbeaf
>+\s+[0-9a-f]+:\s+c5\s+push bc
>+\s+[0-9a-f]+:\s+c6 fd\s+add a,0xfd
>+\s+[0-9a-f]+:\s+c7\s+rst 0x00
>+\s+[0-9a-f]+:\s+c8\s+ret z
>+\s+[0-9a-f]+:\s+c9\s+ret
>+\s+[0-9a-f]+:\s+ca af be\s+jp z,0xbeaf
>+\s+[0-9a-f]+:\s+00\s+nop
>+\s+[0-9a-f]+:\s+cc af be\s+call z,0xbeaf
>+\s+[0-9a-f]+:\s+cd af be\s+call 0xbeaf
>+\s+[0-9a-f]+:\s+ce fd\s+adc a,0xfd
>+\s+[0-9a-f]+:\s+cf\s+rst 0x08
>+\s+[0-9a-f]+:\s+d0\s+ret nc
>+\s+[0-9a-f]+:\s+d1\s+pop de
>+\s+[0-9a-f]+:\s+d2 af be\s+jp nc,0xbeaf
>+\s+[0-9a-f]+:\s+d4 af be\s+call nc,0xbeaf
>+\s+[0-9a-f]+:\s+d5\s+push de
>+\s+[0-9a-f]+:\s+d6 fd\s+sub a,0xfd
>+\s+[0-9a-f]+:\s+d7\s+rst 0x10
>+\s+[0-9a-f]+:\s+d8\s+ret c
>+\s+[0-9a-f]+:\s+d9\s+reti
>+\s+[0-9a-f]+:\s+da af be\s+jp c,0xbeaf
>+\s+[0-9a-f]+:\s+dc af be\s+call c,0xbeaf
>+\s+[0-9a-f]+:\s+de fd\s+sbc a,0xfd
>+\s+[0-9a-f]+:\s+df\s+rst 0x18
>+\s+[0-9a-f]+:\s+e0 fd\s+ldh $0xfd$,a
>+\s+[0-9a-f]+:\s+e1\s+pop hl
>+\s+[0-9a-f]+:\s+e2\s+ldh $c$,a
>+\s+[0-9a-f]+:\s+e5\s+push hl
>+\s+[0-9a-f]+:\s+e6 fd\s+and 0xfd
>+\s+[0-9a-f]+:\s+e7\s+rst 0x20
>+\s+[0-9a-f]+:\s+e8 f4\s+add sp,-12
>+\s+[0-9a-f]+:\s+e9\s+jp $hl$
>+\s+[0-9a-f]+:\s+ea af be\s+ld $0xbeaf$,a
>+\s+[0-9a-f]+:\s+ee fd\s+xor 0xfd
>+\s+[0-9a-f]+:\s+ef\s+rst 0x28
>+\s+[0-9a-f]+:\s+f0 fd\s+ldh a,$0xfd$
>+\s+[0-9a-f]+:\s+f1\s+pop af
>+\s+[0-9a-f]+:\s+f3\s+di
>+\s+[0-9a-f]+:\s+f5\s+push af
>+\s+[0-9a-f]+:\s+f6 fd\s+or 0xfd
>+\s+[0-9a-f]+:\s+f7\s+rst 0x30
>+\s+[0-9a-f]+:\s+f8 f4\s+ldhl sp,-12
>+\s+[0-9a-f]+:\s+f9\s+ld sp,hl
>+\s+[0-9a-f]+:\s+fa af be\s+ld a,$0xbeaf$
>+\s+[0-9a-f]+:\s+fb\s+ei
>+\s+[0-9a-f]+:\s+fe fd\s+cp 0xfd
>+\s+[0-9a-f]+:\s+ff\s+rst 0x38
>+\s+[0-9a-f]+:\s+cb 00\s+rlc b
>+\s+[0-9a-f]+:\s+cb 01\s+rlc c
>+\s+[0-9a-f]+:\s+cb 02\s+rlc d
>+\s+[0-9a-f]+:\s+cb 03\s+rlc e
>+\s+[0-9a-f]+:\s+cb 04\s+rlc h
>+\s+[0-9a-f]+:\s+cb 05\s+rlc l
>+\s+[0-9a-f]+:\s+cb 06\s+rlc $hl$
>+\s+[0-9a-f]+:\s+cb 07\s+rlc a
>+\s+[0-9a-f]+:\s+cb 08\s+rrc b
>+\s+[0-9a-f]+:\s+cb 09\s+rrc c
>+\s+[0-9a-f]+:\s+cb 0a\s+rrc d
>+\s+[0-9a-f]+:\s+cb 0b\s+rrc e
>+\s+[0-9a-f]+:\s+cb 0c\s+rrc h
>+\s+[0-9a-f]+:\s+cb 0d\s+rrc l
>+\s+[0-9a-f]+:\s+cb 0e\s+rrc $hl$
>+\s+[0-9a-f]+:\s+cb 0f\s+rrc a
>+\s+[0-9a-f]+:\s+cb 10\s+rl b
>+\s+[0-9a-f]+:\s+cb 11\s+rl c
>+\s+[0-9a-f]+:\s+cb 12\s+rl d
>+\s+[0-9a-f]+:\s+cb 13\s+rl e
>+\s+[0-9a-f]+:\s+cb 14\s+rl h
>+\s+[0-9a-f]+:\s+cb 15\s+rl l
>+\s+[0-9a-f]+:\s+cb 16\s+rl $hl$
>+\s+[0-9a-f]+:\s+cb 17\s+rl a
>+\s+[0-9a-f]+:\s+cb 18\s+rr b
>+\s+[0-9a-f]+:\s+cb 19\s+rr c
>+\s+[0-9a-f]+:\s+cb 1a\s+rr d
>+\s+[0-9a-f]+:\s+cb 1b\s+rr e
>+\s+[0-9a-f]+:\s+cb 1c\s+rr h
>+\s+[0-9a-f]+:\s+cb 1d\s+rr l
>+\s+[0-9a-f]+:\s+cb 1e\s+rr $hl$
>+\s+[0-9a-f]+:\s+cb 1f\s+rr a
>+\s+[0-9a-f]+:\s+cb 20\s+sla b
>+\s+[0-9a-f]+:\s+cb 21\s+sla c
>+\s+[0-9a-f]+:\s+cb 22\s+sla d
>+\s+[0-9a-f]+:\s+cb 23\s+sla e
>+\s+[0-9a-f]+:\s+cb 24\s+sla h
>+\s+[0-9a-f]+:\s+cb 25\s+sla l
>+\s+[0-9a-f]+:\s+cb 26\s+sla $hl$
>+\s+[0-9a-f]+:\s+cb 27\s+sla a
>+\s+[0-9a-f]+:\s+cb 28\s+sra b
>+\s+[0-9a-f]+:\s+cb 29\s+sra c
>+\s+[0-9a-f]+:\s+cb 2a\s+sra d
>+\s+[0-9a-f]+:\s+cb 2b\s+sra e
>+\s+[0-9a-f]+:\s+cb 2c\s+sra h
>+\s+[0-9a-f]+:\s+cb 2d\s+sra l
>+\s+[0-9a-f]+:\s+cb 2e\s+sra $hl$
>+\s+[0-9a-f]+:\s+cb 2f\s+sra a
>+\s+[0-9a-f]+:\s+cb 30\s+swap b
>+\s+[0-9a-f]+:\s+cb 31\s+swap c
>+\s+[0-9a-f]+:\s+cb 32\s+swap d
>+\s+[0-9a-f]+:\s+cb 33\s+swap e
>+\s+[0-9a-f]+:\s+cb 34\s+swap h
>+\s+[0-9a-f]+:\s+cb 35\s+swap l
>+\s+[0-9a-f]+:\s+cb 36\s+swap $hl$
>+\s+[0-9a-f]+:\s+cb 37\s+swap a
>+\s+[0-9a-f]+:\s+cb 38\s+srl b
>+\s+[0-9a-f]+:\s+cb 39\s+srl c
>+\s+[0-9a-f]+:\s+cb 3a\s+srl d
>+\s+[0-9a-f]+:\s+cb 3b\s+srl e
>+\s+[0-9a-f]+:\s+cb 3c\s+srl h
>+\s+[0-9a-f]+:\s+cb 3d\s+srl l
>+\s+[0-9a-f]+:\s+cb 3e\s+srl $hl$
>+\s+[0-9a-f]+:\s+cb 3f\s+srl a
>+\s+[0-9a-f]+:\s+cb 40\s+bit 0,b
>+\s+[0-9a-f]+:\s+cb 41\s+bit 0,c
>+\s+[0-9a-f]+:\s+cb 42\s+bit 0,d
>+\s+[0-9a-f]+:\s+cb 43\s+bit 0,e
>+\s+[0-9a-f]+:\s+cb 44\s+bit 0,h
>+\s+[0-9a-f]+:\s+cb 45\s+bit 0,l
>+\s+[0-9a-f]+:\s+cb 46\s+bit 0,$hl$
>+\s+[0-9a-f]+:\s+cb 47\s+bit 0,a
>+\s+[0-9a-f]+:\s+cb 48\s+bit 1,b
>+\s+[0-9a-f]+:\s+cb 49\s+bit 1,c
>+\s+[0-9a-f]+:\s+cb 4a\s+bit 1,d
>+\s+[0-9a-f]+:\s+cb 4b\s+bit 1,e
>+\s+[0-9a-f]+:\s+cb 4c\s+bit 1,h
>+\s+[0-9a-f]+:\s+cb 4d\s+bit 1,l
>+\s+[0-9a-f]+:\s+cb 4e\s+bit 1,$hl$
>+\s+[0-9a-f]+:\s+cb 4f\s+bit 1,a
>+\s+[0-9a-f]+:\s+cb 50\s+bit 2,b
>+\s+[0-9a-f]+:\s+cb 51\s+bit 2,c
>+\s+[0-9a-f]+:\s+cb 52\s+bit 2,d
>+\s+[0-9a-f]+:\s+cb 53\s+bit 2,e
>+\s+[0-9a-f]+:\s+cb 54\s+bit 2,h
>+\s+[0-9a-f]+:\s+cb 55\s+bit 2,l
>+\s+[0-9a-f]+:\s+cb 56\s+bit 2,$hl$
>+\s+[0-9a-f]+:\s+cb 57\s+bit 2,a
>+\s+[0-9a-f]+:\s+cb 58\s+bit 3,b
>+\s+[0-9a-f]+:\s+cb 59\s+bit 3,c
>+\s+[0-9a-f]+:\s+cb 5a\s+bit 3,d
>+\s+[0-9a-f]+:\s+cb 5b\s+bit 3,e
>+\s+[0-9a-f]+:\s+cb 5c\s+bit 3,h
>+\s+[0-9a-f]+:\s+cb 5d\s+bit 3,l
>+\s+[0-9a-f]+:\s+cb 5e\s+bit 3,$hl$
>+\s+[0-9a-f]+:\s+cb 5f\s+bit 3,a
>+\s+[0-9a-f]+:\s+cb 60\s+bit 4,b
>+\s+[0-9a-f]+:\s+cb 61\s+bit 4,c
>+\s+[0-9a-f]+:\s+cb 62\s+bit 4,d
>+\s+[0-9a-f]+:\s+cb 63\s+bit 4,e
>+\s+[0-9a-f]+:\s+cb 64\s+bit 4,h
>+\s+[0-9a-f]+:\s+cb 65\s+bit 4,l
>+\s+[0-9a-f]+:\s+cb 66\s+bit 4,$hl$
>+\s+[0-9a-f]+:\s+cb 67\s+bit 4,a
>+\s+[0-9a-f]+:\s+cb 68\s+bit 5,b
>+\s+[0-9a-f]+:\s+cb 69\s+bit 5,c
>+\s+[0-9a-f]+:\s+cb 6a\s+bit 5,d
>+\s+[0-9a-f]+:\s+cb 6b\s+bit 5,e
>+\s+[0-9a-f]+:\s+cb 6c\s+bit 5,h
>+\s+[0-9a-f]+:\s+cb 6d\s+bit 5,l
>+\s+[0-9a-f]+:\s+cb 6e\s+bit 5,$hl$
>+\s+[0-9a-f]+:\s+cb 6f\s+bit 5,a
>+\s+[0-9a-f]+:\s+cb 70\s+bit 6,b
>+\s+[0-9a-f]+:\s+cb 71\s+bit 6,c
>+\s+[0-9a-f]+:\s+cb 72\s+bit 6,d
>+\s+[0-9a-f]+:\s+cb 73\s+bit 6,e
>+\s+[0-9a-f]+:\s+cb 74\s+bit 6,h
>+\s+[0-9a-f]+:\s+cb 75\s+bit 6,l
>+\s+[0-9a-f]+:\s+cb 76\s+bit 6,$hl$
>+\s+[0-9a-f]+:\s+cb 77\s+bit 6,a
>+\s+[0-9a-f]+:\s+cb 78\s+bit 7,b
>+\s+[0-9a-f]+:\s+cb 79\s+bit 7,c
>+\s+[0-9a-f]+:\s+cb 7a\s+bit 7,d
>+\s+[0-9a-f]+:\s+cb 7b\s+bit 7,e
>+\s+[0-9a-f]+:\s+cb 7c\s+bit 7,h
>+\s+[0-9a-f]+:\s+cb 7d\s+bit 7,l
>+\s+[0-9a-f]+:\s+cb 7e\s+bit 7,$hl$
>+\s+[0-9a-f]+:\s+cb 7f\s+bit 7,a
>+\s+[0-9a-f]+:\s+cb 80\s+res 0,b
>+\s+[0-9a-f]+:\s+cb 81\s+res 0,c
>+\s+[0-9a-f]+:\s+cb 82\s+res 0,d
>+\s+[0-9a-f]+:\s+cb 83\s+res 0,e
>+\s+[0-9a-f]+:\s+cb 84\s+res 0,h
>+\s+[0-9a-f]+:\s+cb 85\s+res 0,l
>+\s+[0-9a-f]+:\s+cb 86\s+res 0,$hl$
>+\s+[0-9a-f]+:\s+cb 87\s+res 0,a
>+\s+[0-9a-f]+:\s+cb 88\s+res 1,b
>+\s+[0-9a-f]+:\s+cb 89\s+res 1,c
>+\s+[0-9a-f]+:\s+cb 8a\s+res 1,d
>+\s+[0-9a-f]+:\s+cb 8b\s+res 1,e
>+\s+[0-9a-f]+:\s+cb 8c\s+res 1,h
>+\s+[0-9a-f]+:\s+cb 8d\s+res 1,l
>+\s+[0-9a-f]+:\s+cb 8e\s+res 1,$hl$
>+\s+[0-9a-f]+:\s+cb 8f\s+res 1,a
>+\s+[0-9a-f]+:\s+cb 90\s+res 2,b
>+\s+[0-9a-f]+:\s+cb 91\s+res 2,c
>+\s+[0-9a-f]+:\s+cb 92\s+res 2,d
>+\s+[0-9a-f]+:\s+cb 93\s+res 2,e
>+\s+[0-9a-f]+:\s+cb 94\s+res 2,h
>+\s+[0-9a-f]+:\s+cb 95\s+res 2,l
>+\s+[0-9a-f]+:\s+cb 96\s+res 2,$hl$
>+\s+[0-9a-f]+:\s+cb 97\s+res 2,a
>+\s+[0-9a-f]+:\s+cb 98\s+res 3,b
>+\s+[0-9a-f]+:\s+cb 99\s+res 3,c
>+\s+[0-9a-f]+:\s+cb 9a\s+res 3,d
>+\s+[0-9a-f]+:\s+cb 9b\s+res 3,e
>+\s+[0-9a-f]+:\s+cb 9c\s+res 3,h
>+\s+[0-9a-f]+:\s+cb 9d\s+res 3,l
>+\s+[0-9a-f]+:\s+cb 9e\s+res 3,$hl$
>+\s+[0-9a-f]+:\s+cb 9f\s+res 3,a
>+\s+[0-9a-f]+:\s+cb a0\s+res 4,b
>+\s+[0-9a-f]+:\s+cb a1\s+res 4,c
>+\s+[0-9a-f]+:\s+cb a2\s+res 4,d
>+\s+[0-9a-f]+:\s+cb a3\s+res 4,e
>+\s+[0-9a-f]+:\s+cb a4\s+res 4,h
>+\s+[0-9a-f]+:\s+cb a5\s+res 4,l
>+\s+[0-9a-f]+:\s+cb a6\s+res 4,$hl$
>+\s+[0-9a-f]+:\s+cb a7\s+res 4,a
>+\s+[0-9a-f]+:\s+cb a8\s+res 5,b
>+\s+[0-9a-f]+:\s+cb a9\s+res 5,c
>+\s+[0-9a-f]+:\s+cb aa\s+res 5,d
>+\s+[0-9a-f]+:\s+cb ab\s+res 5,e
>+\s+[0-9a-f]+:\s+cb ac\s+res 5,h
>+\s+[0-9a-f]+:\s+cb ad\s+res 5,l
>+\s+[0-9a-f]+:\s+cb ae\s+res 5,$hl$
>+\s+[0-9a-f]+:\s+cb af\s+res 5,a
>+\s+[0-9a-f]+:\s+cb b0\s+res 6,b
>+\s+[0-9a-f]+:\s+cb b1\s+res 6,c
>+\s+[0-9a-f]+:\s+cb b2\s+res 6,d
>+\s+[0-9a-f]+:\s+cb b3\s+res 6,e
>+\s+[0-9a-f]+:\s+cb b4\s+res 6,h
>+\s+[0-9a-f]+:\s+cb b5\s+res 6,l
>+\s+[0-9a-f]+:\s+cb b6\s+res 6,$hl$
>+\s+[0-9a-f]+:\s+cb b7\s+res 6,a
>+\s+[0-9a-f]+:\s+cb b8\s+res 7,b
>+\s+[0-9a-f]+:\s+cb b9\s+res 7,c
>+\s+[0-9a-f]+:\s+cb ba\s+res 7,d
>+\s+[0-9a-f]+:\s+cb bb\s+res 7,e
>+\s+[0-9a-f]+:\s+cb bc\s+res 7,h
>+\s+[0-9a-f]+:\s+cb bd\s+res 7,l
>+\s+[0-9a-f]+:\s+cb be\s+res 7,$hl$
>+\s+[0-9a-f]+:\s+cb bf\s+res 7,a
>+\s+[0-9a-f]+:\s+cb c0\s+set 0,b
>+\s+[0-9a-f]+:\s+cb c1\s+set 0,c
>+\s+[0-9a-f]+:\s+cb c2\s+set 0,d
>+\s+[0-9a-f]+:\s+cb c3\s+set 0,e
>+\s+[0-9a-f]+:\s+cb c4\s+set 0,h
>+\s+[0-9a-f]+:\s+cb c5\s+set 0,l
>+\s+[0-9a-f]+:\s+cb c6\s+set 0,$hl$
>+\s+[0-9a-f]+:\s+cb c7\s+set 0,a
>+\s+[0-9a-f]+:\s+cb c8\s+set 1,b
>+\s+[0-9a-f]+:\s+cb c9\s+set 1,c
>+\s+[0-9a-f]+:\s+cb ca\s+set 1,d
>+\s+[0-9a-f]+:\s+cb cb\s+set 1,e
>+\s+[0-9a-f]+:\s+cb cc\s+set 1,h
>+\s+[0-9a-f]+:\s+cb cd\s+set 1,l
>+\s+[0-9a-f]+:\s+cb ce\s+set 1,$hl$
>+\s+[0-9a-f]+:\s+cb cf\s+set 1,a
>+\s+[0-9a-f]+:\s+cb d0\s+set 2,b
>+\s+[0-9a-f]+:\s+cb d1\s+set 2,c
>+\s+[0-9a-f]+:\s+cb d2\s+set 2,d
>+\s+[0-9a-f]+:\s+cb d3\s+set 2,e
>+\s+[0-9a-f]+:\s+cb d4\s+set 2,h
>+\s+[0-9a-f]+:\s+cb d5\s+set 2,l
>+\s+[0-9a-f]+:\s+cb d6\s+set 2,$hl$
>+\s+[0-9a-f]+:\s+cb d7\s+set 2,a
>+\s+[0-9a-f]+:\s+cb d8\s+set 3,b
>+\s+[0-9a-f]+:\s+cb d9\s+set 3,c
>+\s+[0-9a-f]+:\s+cb da\s+set 3,d
>+\s+[0-9a-f]+:\s+cb db\s+set 3,e
>+\s+[0-9a-f]+:\s+cb dc\s+set 3,h
>+\s+[0-9a-f]+:\s+cb dd\s+set 3,l
>+\s+[0-9a-f]+:\s+cb de\s+set 3,$hl$
>+\s+[0-9a-f]+:\s+cb df\s+set 3,a
>+\s+[0-9a-f]+:\s+cb e0\s+set 4,b
>+\s+[0-9a-f]+:\s+cb e1\s+set 4,c
>+\s+[0-9a-f]+:\s+cb e2\s+set 4,d
>+\s+[0-9a-f]+:\s+cb e3\s+set 4,e
>+\s+[0-9a-f]+:\s+cb e4\s+set 4,h
>+\s+[0-9a-f]+:\s+cb e5\s+set 4,l
>+\s+[0-9a-f]+:\s+cb e6\s+set 4,$hl$
>+\s+[0-9a-f]+:\s+cb e7\s+set 4,a
>+\s+[0-9a-f]+:\s+cb e8\s+set 5,b
>+\s+[0-9a-f]+:\s+cb e9\s+set 5,c
>+\s+[0-9a-f]+:\s+cb ea\s+set 5,d
>+\s+[0-9a-f]+:\s+cb eb\s+set 5,e
>+\s+[0-9a-f]+:\s+cb ec\s+set 5,h
>+\s+[0-9a-f]+:\s+cb ed\s+set 5,l
>+\s+[0-9a-f]+:\s+cb ee\s+set 5,$hl$
>+\s+[0-9a-f]+:\s+cb ef\s+set 5,a
>+\s+[0-9a-f]+:\s+cb f0\s+set 6,b
>+\s+[0-9a-f]+:\s+cb f1\s+set 6,c
>+\s+[0-9a-f]+:\s+cb f2\s+set 6,d
>+\s+[0-9a-f]+:\s+cb f3\s+set 6,e
>+\s+[0-9a-f]+:\s+cb f4\s+set 6,h
>+\s+[0-9a-f]+:\s+cb f5\s+set 6,l
>+\s+[0-9a-f]+:\s+cb f6\s+set 6,$hl$
>+\s+[0-9a-f]+:\s+cb f7\s+set 6,a
>+\s+[0-9a-f]+:\s+cb f8\s+set 7,b
>+\s+[0-9a-f]+:\s+cb f9\s+set 7,c
>+\s+[0-9a-f]+:\s+cb fa\s+set 7,d
>+\s+[0-9a-f]+:\s+cb fb\s+set 7,e
>+\s+[0-9a-f]+:\s+cb fc\s+set 7,h
>+\s+[0-9a-f]+:\s+cb fd\s+set 7,l
>+\s+[0-9a-f]+:\s+cb fe\s+set 7,$hl$
>+\s+[0-9a-f]+:\s+cb ff\s+set 7,a
>diff --git a/gas/testsuite/gas/z80/gbz80_all.s b/gas/testsuite/gas/z80/gbz80_all.s
>new file mode 100644
>index 0000000000..1a09f83813
>--- /dev/null
>+++ b/gas/testsuite/gas/z80/gbz80_all.s
>@@ -0,0 +1,515 @@
>+	.text
>+	.org	0
>+;;	Game	Boy	Z80	opcode	test
>+	nop
>+	ld	bc,0xbeaf
>+	ld	(bc),a
>+	inc	bc
>+	inc	b
>+	dec	b
>+	ld	b,0xfd
>+	rlca
>+	ld	(0xbeaf),sp
>+	add	hl,bc
>+	ld	a,(bc)
>+	dec	bc
>+	inc	c
>+	dec	c
>+	ld	c,0xfd
>+	rrca
>+	stop
>+	ld	de,0xbeaf
>+	ld	(de),a
>+	inc	de
>+	inc	d
>+	dec	d
>+	ld	d,0xfd
>+	rla
>+	jr	.+12
>+	add	hl,de
>+	ld	a,(de)
>+	dec	de
>+	inc	e
>+	dec	e
>+	ld	e,0xfd
>+	rra
>+	jr	nz,.+12
>+	ld	hl,0xbeaf
>+	ldi	(hl),a
>+	inc	hl
>+	inc	h
>+	dec	h
>+	ld	h,0xfd
>+	daa
>+	jr	z,.+12
>+	add	hl,hl
>+	ldi	a,(hl)
>+	dec	hl
>+	inc	l
>+	dec	l
>+	ld	l,0xfd
>+	cpl
>+	jr	nc,.+12
>+	ld	sp,0xbeaf
>+	ldd	(hl),a
>+	inc	sp
>+	inc	(hl)
>+	dec	(hl)
>+	ld	(hl),0xfd
>+	scf
>+	jr	c,.+12
>+	add	hl,sp
>+	ldd	a,(hl)
>+	dec	sp
>+	inc	a
>+	dec	a
>+	ld	a,0xfd
>+	ccf
>+	ld	b,b
>+	ld	b,c
>+	ld	b,d
>+	ld	b,e
>+	ld	b,h
>+	ld	b,l
>+	ld	b,(hl)
>+	ld	b,a
>+	ld	c,b
>+	ld	c,c
>+	ld	c,d
>+	ld	c,e
>+	ld	c,h
>+	ld	c,l
>+	ld	c,(hl)
>+	ld	c,a
>+	ld	d,b
>+	ld	d,c
>+	ld	d,d
>+	ld	d,e
>+	ld	d,h
>+	ld	d,l
>+	ld	d,(hl)
>+	ld	d,a
>+	ld	e,b
>+	ld	e,c
>+	ld	e,d
>+	ld	e,e
>+	ld	e,h
>+	ld	e,l
>+	ld	e,(hl)
>+	ld	e,a
>+	ld	h,b
>+	ld	h,c
>+	ld	h,d
>+	ld	h,e
>+	ld	h,h
>+	ld	h,l
>+	ld	h,(hl)
>+	ld	h,a
>+	ld	l,b
>+	ld	l,c
>+	ld	l,d
>+	ld	l,e
>+	ld	l,h
>+	ld	l,l
>+	ld	l,(hl)
>+	ld	l,a
>+	ld	(hl),b
>+	ld	(hl),c
>+	ld	(hl),d
>+	ld	(hl),e
>+	ld	(hl),h
>+	ld	(hl),l
>+	halt
>+	ld	(hl),a
>+	ld	a,b
>+	ld	a,c
>+	ld	a,d
>+	ld	a,e
>+	ld	a,h
>+	ld	a,l
>+	ld	a,(hl)
>+	ld	a,a
>+	add	a,b
>+	add	a,c
>+	add	a,d
>+	add	a,e
>+	add	a,h
>+	add	a,l
>+	add	a,(hl)
>+	add	a,a
>+	adc	a,b
>+	adc	a,c
>+	adc	a,d
>+	adc	a,e
>+	adc	a,h
>+	adc	a,l
>+	adc	a,(hl)
>+	adc	a,a
>+	sub	a,b
>+	sub	a,c
>+	sub	a,d
>+	sub	a,e
>+	sub	a,h
>+	sub	a,l
>+	sub	a,(hl)
>+	sub	a,a
>+	sbc	a,b
>+	sbc	a,c
>+	sbc	a,d
>+	sbc	a,e
>+	sbc	a,h
>+	sbc	a,l
>+	sbc	a,(hl)
>+	sbc	a,a
>+	and	b
>+	and	c
>+	and	d
>+	and	e
>+	and	h
>+	and	l
>+	and	(hl)
>+	and	a
>+	xor	b
>+	xor	c
>+	xor	d
>+	xor	e
>+	xor	h
>+	xor	l
>+	xor	(hl)
>+	xor	a
>+	or	b
>+	or	c
>+	or	d
>+	or	e
>+	or	h
>+	or	l
>+	or	(hl)
>+	or	a
>+	cp	b
>+	cp	c
>+	cp	d
>+	cp	e
>+	cp	h
>+	cp	l
>+	cp	(hl)
>+	cp	a
>+	ret	nz
>+	pop	bc
>+	jp	nz,0xbeaf
>+	jp	0xbeaf
>+	call	nz,0xbeaf
>+	push	bc
>+	add	a,0xfd
>+	rst	0
>+	ret	z
>+	ret
>+	jp	z,0xbeaf
>+	nop		;CB prefix
>+	call	z,0xbeaf
>+	call	0xbeaf
>+	adc	a,0xfd
>+	rst	0x08
>+	ret	nc
>+	pop	de
>+	jp	nc,0xbeaf
>+	;xx
>+	call	nc,0xbeaf
>+	push	de
>+	sub	a,0xfd
>+	rst	0x10
>+	ret	c
>+	reti
>+	jp	c,0xbeaf
>+	;xx
>+	call	c,0xbeaf
>+	;xx
>+	sbc	a,0xfd
>+	rst	0x18
>+	ldh	(0xfd),a
>+	pop	hl
>+	ldh	(c),a
>+	;xx
>+	;xx
>+	push	hl
>+	and	0xfd
>+	rst	0x20
>+	add	sp,-12
>+	jp	(hl)
>+	ld	(0xbeaf),a
>+	;xx
>+	;xx
>+	;xx
>+	xor	0xfd
>+	rst	0x28
>+	ldh	a,(0xfd)
>+	pop	af
>+	;xx
>+	di
>+	;xx
>+	push	af
>+	or	0xfd
>+	rst	0x30
>+	ldhl	sp,-12
>+	ld	sp,hl
>+	ld	a,(0xbeaf)
>+	ei
>+	;xx
>+	;xx
>+	cp	0xfd
>+	rst	0x38
>+	rlc	b
>+	rlc	c
>+	rlc	d
>+	rlc	e
>+	rlc	h
>+	rlc	l
>+	rlc	(hl)
>+	rlc	a
>+	rrc	b
>+	rrc	c
>+	rrc	d
>+	rrc	e
>+	rrc	h
>+	rrc	l
>+	rrc	(hl)
>+	rrc	a
>+	rl	b
>+	rl	c
>+	rl	d
>+	rl	e
>+	rl	h
>+	rl	l
>+	rl	(hl)
>+	rl	a
>+	rr	b
>+	rr	c
>+	rr	d
>+	rr	e
>+	rr	h
>+	rr	l
>+	rr	(hl)
>+	rr	a
>+	sla	b
>+	sla	c
>+	sla	d
>+	sla	e
>+	sla	h
>+	sla	l
>+	sla	(hl)
>+	sla	a
>+	sra	b
>+	sra	c
>+	sra	d
>+	sra	e
>+	sra	h
>+	sra	l
>+	sra	(hl)
>+	sra	a
>+	swap	b
>+	swap	c
>+	swap	d
>+	swap	e
>+	swap	h
>+	swap	l
>+	swap	(hl)
>+	swap	a
>+	srl	b
>+	srl	c
>+	srl	d
>+	srl	e
>+	srl	h
>+	srl	l
>+	srl	(hl)
>+	srl	a
>+	bit	0,b
>+	bit	0,c
>+	bit	0,d
>+	bit	0,e
>+	bit	0,h
>+	bit	0,l
>+	bit	0,(hl)
>+	bit	0,a
>+	bit	1,b
>+	bit	1,c
>+	bit	1,d
>+	bit	1,e
>+	bit	1,h
>+	bit	1,l
>+	bit	1,(hl)
>+	bit	1,a
>+	bit	2,b
>+	bit	2,c
>+	bit	2,d
>+	bit	2,e
>+	bit	2,h
>+	bit	2,l
>+	bit	2,(hl)
>+	bit	2,a
>+	bit	3,b
>+	bit	3,c
>+	bit	3,d
>+	bit	3,e
>+	bit	3,h
>+	bit	3,l
>+	bit	3,(hl)
>+	bit	3,a
>+	bit	4,b
>+	bit	4,c
>+	bit	4,d
>+	bit	4,e
>+	bit	4,h
>+	bit	4,l
>+	bit	4,(hl)
>+	bit	4,a
>+	bit	5,b
>+	bit	5,c
>+	bit	5,d
>+	bit	5,e
>+	bit	5,h
>+	bit	5,l
>+	bit	5,(hl)
>+	bit	5,a
>+	bit	6,b
>+	bit	6,c
>+	bit	6,d
>+	bit	6,e
>+	bit	6,h
>+	bit	6,l
>+	bit	6,(hl)
>+	bit	6,a
>+	bit	7,b
>+	bit	7,c
>+	bit	7,d
>+	bit	7,e
>+	bit	7,h
>+	bit	7,l
>+	bit	7,(hl)
>+	bit	7,a
>+	res	0,b
>+	res	0,c
>+	res	0,d
>+	res	0,e
>+	res	0,h
>+	res	0,l
>+	res	0,(hl)
>+	res	0,a
>+	res	1,b
>+	res	1,c
>+	res	1,d
>+	res	1,e
>+	res	1,h
>+	res	1,l
>+	res	1,(hl)
>+	res	1,a
>+	res	2,b
>+	res	2,c
>+	res	2,d
>+	res	2,e
>+	res	2,h
>+	res	2,l
>+	res	2,(hl)
>+	res	2,a
>+	res	3,b
>+	res	3,c
>+	res	3,d
>+	res	3,e
>+	res	3,h
>+	res	3,l
>+	res	3,(hl)
>+	res	3,a
>+	res	4,b
>+	res	4,c
>+	res	4,d
>+	res	4,e
>+	res	4,h
>+	res	4,l
>+	res	4,(hl)
>+	res	4,a
>+	res	5,b
>+	res	5,c
>+	res	5,d
>+	res	5,e
>+	res	5,h
>+	res	5,l
>+	res	5,(hl)
>+	res	5,a
>+	res	6,b
>+	res	6,c
>+	res	6,d
>+	res	6,e
>+	res	6,h
>+	res	6,l
>+	res	6,(hl)
>+	res	6,a
>+	res	7,b
>+	res	7,c
>+	res	7,d
>+	res	7,e
>+	res	7,h
>+	res	7,l
>+	res	7,(hl)
>+	res	7,a
>+	set	0,b
>+	set	0,c
>+	set	0,d
>+	set	0,e
>+	set	0,h
>+	set	0,l
>+	set	0,(hl)
>+	set	0,a
>+	set	1,b
>+	set	1,c
>+	set	1,d
>+	set	1,e
>+	set	1,h
>+	set	1,l
>+	set	1,(hl)
>+	set	1,a
>+	set	2,b
>+	set	2,c
>+	set	2,d
>+	set	2,e
>+	set	2,h
>+	set	2,l
>+	set	2,(hl)
>+	set	2,a
>+	set	3,b
>+	set	3,c
>+	set	3,d
>+	set	3,e
>+	set	3,h
>+	set	3,l
>+	set	3,(hl)
>+	set	3,a
>+	set	4,b
>+	set	4,c
>+	set	4,d
>+	set	4,e
>+	set	4,h
>+	set	4,l
>+	set	4,(hl)
>+	set	4,a
>+	set	5,b
>+	set	5,c
>+	set	5,d
>+	set	5,e
>+	set	5,h
>+	set	5,l
>+	set	5,(hl)
>+	set	5,a
>+	set	6,b
>+	set	6,c
>+	set	6,d
>+	set	6,e
>+	set	6,h
>+	set	6,l
>+	set	6,(hl)
>+	set	6,a
>+	set	7,b
>+	set	7,c
>+	set	7,d
>+	set	7,e
>+	set	7,h
>+	set	7,l
>+	set	7,(hl)
>+	set	7,a
>diff --git a/gas/testsuite/gas/z80/z80.exp b/gas/testsuite/gas/z80/z80.exp
>index 6ba13fc0ac..e4209d1fd3 100644
>--- a/gas/testsuite/gas/z80/z80.exp
>+++ b/gas/testsuite/gas/z80/z80.exp
>@@ -92,6 +92,8 @@ if [istarget z80-*-*] then {
>     run_dump_test "ez80_adl_suf"
> #test for eZ80 opcode prefixes as multiple bytes before instruction
>     run_dump_test "ez80_pref_dis"
>+#test for GBZ80 instruction set
>+    run_dump_test "gbz80_all"
> # test for SDCC compatibility mode
>     run_dump_test "sdcc"
> # test for colonless labels
>diff --git a/opcodes/z80-dis.c b/opcodes/z80-dis.c
>index 7dfb5f2bd9..9d7f14ab3a 100644
>--- a/opcodes/z80-dis.c
>+++ b/opcodes/z80-dis.c
>@@ -65,6 +65,10 @@ static const char * arit_str[] =
> {
>   "add a,", "adc a,", "sub ", "sbc a,", "and ", "xor ", "or ", "cp "
> } ;
>+static const char * arit_str_gbz80[] =
>+{
>+  "add a,", "adc a,", "sub a,", "sbc a,", "and ", "xor ", "or ", "cp "
>+} ;
> static const char * arit_str_ez80[] =
> {
>   "add a,", "adc a,", "sub a,", "sbc a,", "and a,", "xor a,", "or a,", "cp a,"
>@@ -72,7 +76,7 @@ static const char * arit_str_ez80[] =
> 
> 
> static int
>-mach_inst (struct buffer *buf, struct tab_elt *p)
>+mach_inst (struct buffer *buf, const struct tab_elt *p)
> {
>   return !p->inss || (p->inss & buf->inss);
> }
>@@ -268,7 +272,14 @@ static int
> arit_r (struct buffer *buf, disassemble_info * info, const char *txt)
> {
>   const char * const *arit;
>-  arit = (buf->inss & INSS_EZ80) ? arit_str_ez80 : arit_str;
>+
>+  if (buf->inss & INSS_EZ80)
>+    arit = arit_str_ez80;
>+  else if (buf->inss & INSS_GBZ80)
>+    arit = arit_str_gbz80;
>+  else
>+    arit = arit_str;
>+
>   info->fprintf_func (info->stream, txt,
>                       arit[(buf->data[buf->n_fetch - 1] >> 3) & 7],
>                       r_str[buf->data[buf->n_fetch - 1] & 7]);
>@@ -313,7 +324,13 @@ arit_n (struct buffer *buf, disassemble_info * info, const char *txt)
>   char mytxt[TXTSIZ];
>   const char * const *arit;
> 
>-  arit = (buf->inss & INSS_EZ80) ? arit_str_ez80 : arit_str;
>+  if (buf->inss & INSS_EZ80)
>+    arit = arit_str_ez80;
>+  else if (buf->inss & INSS_GBZ80)
>+    arit = arit_str_gbz80;
>+  else
>+    arit = arit_str;
>+
>   snprintf (mytxt,TXTSIZ, txt, arit[(buf->data[0] >> 3) & 7]);
>   return prt_n (buf, info, mytxt);
> }
>@@ -326,7 +343,7 @@ rst (struct buffer *buf, disassemble_info * info, const char *txt)
>   return buf->n_used;
> }
> 
>-
>+
> static int
> cis (struct buffer *buf, disassemble_info * info, const char *txt ATTRIBUTE_UNUSED)
> {
>@@ -391,7 +408,7 @@ dump (struct buffer *buf, disassemble_info * info, const char *txt)
>   buf->n_used = i;
>   return buf->n_used;
> }
>-
>+
> /* Table to disassemble machine codes with prefix 0xED.  */
> struct tab_elt opc_ed[] =
> {
>@@ -521,7 +538,7 @@ pref_cb (struct buffer *buf, disassemble_info *info,
> 
>   return buf->n_used;
> }
>-
>+
> static int
> addvv (struct buffer * buf, disassemble_info * info, const char *txt)
> {
>@@ -767,7 +784,8 @@ suffix (struct buffer *buf, disassemble_info *info, const char *txt)
> }
> 
> /* Table to disassemble machine codes without prefix.  */
>-static struct tab_elt opc_main[] =
>+static const struct tab_elt
>+opc_main[] =
> {
>   { 0x00, 0xFF, prt, "nop", INSS_ALL },
>   { 0x01, 0xCF, prt_rr_nn, "ld %s,0x%%04x", INSS_ALL },
>@@ -829,12 +847,73 @@ static struct tab_elt opc_main[] =
>   { 0xEB, 0xFF, prt, "ex de,hl", ~INSS_GBZ80 },
>   { 0xED, 0xFF, pref_ed, "", ~INSS_GBZ80 },
>   { 0xF3, 0xFF, prt, "di", INSS_ALL },
>-  { 0xF9, 0xFF, prt, "ld sp,hl", ~INSS_GBZ80 },
>+  { 0xF9, 0xFF, prt, "ld sp,hl", INSS_ALL },
>   { 0xFB, 0xFF, prt, "ei", INSS_ALL },
>   { 0xFD, 0xFF, pref_ind, "iy", ~INSS_GBZ80 },
>   { 0x00, 0x00, prt, "????", INSS_ALL },
> } ;
> 
>+/* Separate GBZ80 main opcode table due to many differences */
>+static const struct tab_elt
>+opc_main_gbz80[] =
>+{
>+  { 0x00, 0xFF, prt,"nop", INSS_ALL },
>+  { 0x01, 0xCF, prt_rr_nn, "ld %s,0x%%04x", INSS_ALL },
>+  { 0x02, 0xFF, prt, "ld (bc),a", INSS_ALL },
>+  { 0x03, 0xCF, prt_rr, "inc ", INSS_ALL },
>+  { 0x04, 0xC7, prt_r, "inc %s", INSS_ALL },
>+  { 0x05, 0xC7, prt_r, "dec %s", INSS_ALL },
>+  { 0x06, 0xC7, ld_r_n, "ld %s,0x%%02x", INSS_ALL },
>+  { 0x07, 0xFF, prt, "rlca", INSS_ALL },
>+  { 0x08, 0xFF, prt_nn, "ld (0x%04x),sp", INSS_GBZ80 },
>+  { 0x09, 0xCF, prt_rr, "add hl,", INSS_ALL },
>+  { 0x0A, 0xFF, prt, "ld a,(bc)", INSS_ALL },
>+  { 0x0B, 0xCF, prt_rr, "dec ", INSS_ALL },
>+  { 0x0F, 0xFF, prt, "rrca", INSS_ALL },
>+  { 0x10, 0xFF, prt, "stop", INSS_GBZ80 },
>+  { 0x12, 0xFF, prt, "ld (de),a", INSS_ALL },
>+  { 0x17, 0xFF, prt, "rla", INSS_ALL },
>+  { 0x18, 0xFF, prt_e, "jr ", INSS_ALL },
>+  { 0x1A, 0xFF, prt, "ld a,(de)", INSS_ALL },
>+  { 0x1F, 0xFF, prt, "rra", INSS_ALL },
>+  { 0x20, 0xE7, jr_cc, "jr %s,", INSS_ALL },
>+  { 0x22, 0xFF, prt, "ldi (hl),a", INSS_GBZ80 },
>+  { 0x27, 0xFF, prt, "daa", INSS_ALL },
>+  { 0x2A, 0xFF, prt, "ldi a,(hl)", INSS_GBZ80 },
>+  { 0x2F, 0xFF, prt, "cpl", INSS_ALL },
>+  { 0x32, 0xFF, prt, "ldd (hl),a", INSS_GBZ80 },
>+  { 0x37, 0xFF, prt, "scf", INSS_ALL },
>+  { 0x3A, 0xFF, prt, "ldd a,(hl)", INSS_GBZ80 },
>+  { 0x3F, 0xFF, prt, "ccf", INSS_ALL },
>+  { 0x76, 0xFF, prt, "halt", INSS_ALL },
>+  { 0x40, 0xC0, ld_r_r, "ld %s,%s", INSS_ALL},
>+  { 0x80, 0xC0, arit_r, "%s%s", INSS_ALL },
>+  { 0xC0, 0xE7, prt_cc, "ret ", INSS_ALL },
>+  { 0xC1, 0xCF, pop_rr, "pop", INSS_ALL },
>+  { 0xC2, 0xE7, jp_cc_nn, "jp ", INSS_ALL },
>+  { 0xC3, 0xFF, prt_nn, "jp 0x%04x", INSS_ALL },
>+  { 0xC4, 0xE7, jp_cc_nn, "call ", INSS_ALL },
>+  { 0xC5, 0xCF, pop_rr, "push", INSS_ALL },
>+  { 0xC6, 0xC7, arit_n, "%s0x%%02x", INSS_ALL },
>+  { 0xC7, 0xC7, rst, "rst 0x%02x", INSS_ALL },
>+  { 0xC9, 0xFF, prt, "ret", INSS_ALL },
>+  { 0xCB, 0xFF, pref_cb, "", INSS_ALL },
>+  { 0xCD, 0xFF, prt_nn, "call 0x%04x", INSS_ALL },
>+  { 0xD9, 0xFF, prt, "reti", INSS_GBZ80 },
>+  { 0xE0, 0xFF, prt_n, "ldh (0x%02x),a", INSS_GBZ80 },
>+  { 0xE2, 0xFF, prt, "ldh (c),a", INSS_GBZ80 },
>+  { 0xE8, 0xFF, prt_d, "add sp,%d", INSS_GBZ80 },
>+  { 0xE9, 0xFF, prt, "jp (hl)", INSS_ALL },
>+  { 0xEA, 0xFF, prt_nn, "ld (0x%04x),a", INSS_GBZ80 },
>+  { 0xF0, 0xFF, prt_n, "ldh a,(0x%02x)", INSS_GBZ80 },
>+  { 0xF3, 0xFF, prt, "di", INSS_ALL },
>+  { 0xF8, 0xFF, prt_d, "ldhl sp,%d", INSS_GBZ80 },
>+  { 0xF9, 0xFF, prt, "ld sp,hl", INSS_ALL },
>+  { 0xFA, 0xFF, prt_nn, "ld a,(0x%04x)", INSS_GBZ80 },
>+  { 0xFB, 0xFF, prt, "ei", INSS_ALL },
>+  { 0x00, 0x00, dump, "?", INSS_ALL },
>+} ;
>+
> int
> print_insn_z80 (bfd_vma addr, disassemble_info * info)
> {
>@@ -851,14 +930,16 @@ print_insn_z80 (bfd_vma addr, disassemble_info * info)
> static int
> print_insn_z80_buf (struct buffer *buf, disassemble_info *info)
> {
>-  struct tab_elt *p;
>+  const struct tab_elt *p;
> 
>   buf->n_fetch = 0;
>   buf->n_used = 0;
>   if (! fetch_data (buf, info, 1))
>     return -1;
> 
>-  for (p = opc_main; p->val != (buf->data[0] & p->mask) || !mach_inst (buf, p); ++p)
>+  p = (buf->inss & INSS_GBZ80) ? opc_main_gbz80 : opc_main;
>+
>+  for (; p->val != (buf->data[0] & p->mask) || !mach_inst (buf, p); ++p)
>     ;
>   p->fp (buf, info, p->text);
> 
>-- 
>2.17.1
>
>
>From 9cbc5fe70f5b17033dc8bcf52f1d2ff7c7705faf Mon Sep 17 00:00:00 2001
>From: Sergey Belyashov <Sergey.Belyashov@gmail.com>
>Date: Wed, 29 Jan 2020 12:31:15 +0300
>Subject: [PATCH 2/7] [Z80] Enable gc-sections and DWARF
>
>---
> bfd/elf32-z80.c     |  2 ++
> gas/config/tc-z80.c | 32 ++++++++++++++++++++++++++++++++
> gas/config/tc-z80.h | 22 ++++++++++++++++++++++
> 3 files changed, 56 insertions(+)
>
>diff --git a/bfd/elf32-z80.c b/bfd/elf32-z80.c
>index 888606e7b5..c873a8df19 100644
>--- a/bfd/elf32-z80.c
>+++ b/bfd/elf32-z80.c
>@@ -372,6 +372,8 @@ z80_is_local_label_name (bfd *        abfd ATTRIBUTE_UNUSED,
> #define TARGET_LITTLE_SYM		z80_elf32_vec
> #define TARGET_LITTLE_NAME		"elf32-z80"
> 
>+#define elf_backend_can_gc_sections		1
>+
> #define elf_info_to_howto			NULL
> #define elf_info_to_howto_rel			z80_info_to_howto_rel
> #define elf_backend_object_p			z80_elf_set_mach_from_flags
>diff --git a/gas/config/tc-z80.c b/gas/config/tc-z80.c
>index 468e21f7b3..02aa2367d2 100644
>--- a/gas/config/tc-z80.c
>+++ b/gas/config/tc-z80.c
>@@ -24,6 +24,7 @@
> #include "subsegs.h"
> #include "elf/z80.h"
> #include "dwarf2dbg.h"
>+#include "dw2gencfi.h"
> 
> /* Exported constants.  */
> const char comment_chars[] = ";\0";
>@@ -3762,3 +3763,34 @@ str_to_ieee754_d(char *litP, int *sizeP)
> {
>   return ieee_md_atof ('d', litP, sizeP, FALSE);
> }
>+
>+/* Initialize the DWARF-2 unwind information for this procedure. */
>+void
>+z80_tc_frame_initial_instructions (void)
>+{
>+  static int sp_regno = -1;
>+
>+  if (sp_regno < 0)
>+    sp_regno = z80_tc_regname_to_dw2regnum ("sp");
>+
>+  cfi_add_CFA_def_cfa (sp_regno, 0);
>+}
>+
>+int
>+z80_tc_regname_to_dw2regnum (const char *regname)
>+{
>+  static const char *regs[] =
>+    { /* same registers as for GDB */
>+      "af", "bc", "de", "hl",
>+      "ix", "iy", "sp", "pc",
>+      "af_", "bc_", "de_", "hl_",
>+      "ir", "mbst" /* MB - eZ80 register, ST: bit0 - iff1, bit1 - iff2, bit2 - ADL, bit3 - MADL */
>+    };
>+  unsigned i;
>+
>+  for (i = 0; i < ARRAY_SIZE(regs); ++i)
>+    if (!strcasecmp (regs[i], regname))
>+      return i;
>+
>+  return -1;
>+}
>diff --git a/gas/config/tc-z80.h b/gas/config/tc-z80.h
>index 5749027091..5ce638d459 100644
>--- a/gas/config/tc-z80.h
>+++ b/gas/config/tc-z80.h
>@@ -116,4 +116,26 @@ extern int z80_tc_label_is_local (const char *name);
> #define elf_tc_final_processing	z80_elf_final_processing
> extern void z80_elf_final_processing (void);
> 
>+/* Define the column that represents the PC.  */
>+#define DWARF2_DEFAULT_RETURN_COLUMN	7
>+
>+/* The stack grows down, and is only byte aligned.  */
>+#define DWARF2_CIE_DATA_ALIGNMENT	-1
>+
>+/* We want .cfi_* pseudo-ops for generating unwind info.  */
>+#define TARGET_USE_CFIPOP		1
>+
>+/* Z80 instructions are 1 or 4 bytes long.  */
>+#define DWARF2_LINE_MIN_INSN_LENGTH	1
>+
>+/* 16 bits addresses are used on Z80.  */
>+#define DWARF2_ADDR_SIZE(bfd)		2
>+
>+/* CFI hooks.  */
>+#define tc_cfi_frame_initial_instructions z80_tc_frame_initial_instructions
>+extern void z80_tc_frame_initial_instructions (void);
>+
>+#define tc_regname_to_dw2regnum z80_tc_regname_to_dw2regnum
>+extern int z80_tc_regname_to_dw2regnum (const char *regname);
>+
> #endif
>-- 
>2.17.1
>
>
>From 0ada970915c64a2fff46d12523e962fbc9ed371c Mon Sep 17 00:00:00 2001
>From: Sergey Belyashov <Sergey.Belyashov@gmail.com>
>Date: Wed, 29 Jan 2020 19:00:48 +0300
>Subject: [PATCH 3/7] [Z80] Add Z80N CPU support
>
>---
> bfd/archures.c                           |   17 +-
> bfd/bfd-in2.h                            |   18 +-
> bfd/coff-z80.c                           |   26 +
> bfd/coffcode.h                           |    2 +
> bfd/cpu-z80.c                            |    3 +-
> bfd/elf32-z80.c                          |   74 ++
> bfd/libbfd.h                             |    1 +
> bfd/reloc.c                              |    4 +
> binutils/readelf.c                       |    1 +
> gas/config/tc-z80.c                      |  291 ++++-
> gas/config/tc-z80.h                      |    2 +-
> gas/doc/c-z80.texi                       |   18 +-
> gas/testsuite/gas/z80/z80.exp            |    4 +
> gas/testsuite/gas/z80/z80n_all.d         | 1208 +++++++++++++++++++++
> gas/testsuite/gas/z80/z80n_all.s         | 1242 ++++++++++++++++++++++
> gas/testsuite/gas/z80/z80n_reloc.d       |   10 +
> include/coff/internal.h                  |    1 +
> include/elf/z80.h                        |    2 +
> ld/emultempl/z80.em                      |    9 +-
> ld/emultempl/z80elf.em                   |  157 +--
> ld/testsuite/ld-z80/arch_z80n.d          |   11 +
> ld/testsuite/ld-z80/comb_arch_z80_z80n.d |   11 +
> ld/testsuite/ld-z80/labels.s             |    6 +
> ld/testsuite/ld-z80/relocs.s             |   11 +
> ld/testsuite/ld-z80/relocs_f_z80n.d      |   86 ++
> opcodes/z80-dis.c                        |   71 +-
> 26 files changed, 3159 insertions(+), 127 deletions(-)
> create mode 100644 gas/testsuite/gas/z80/z80n_all.d
> create mode 100644 gas/testsuite/gas/z80/z80n_all.s
> create mode 100644 gas/testsuite/gas/z80/z80n_reloc.d
> create mode 100644 ld/testsuite/ld-z80/arch_z80n.d
> create mode 100644 ld/testsuite/ld-z80/comb_arch_z80_z80n.d
> create mode 100644 ld/testsuite/ld-z80/relocs_f_z80n.d
>
>diff --git a/bfd/archures.c b/bfd/archures.c
>index 232103817c..c4b3d083c9 100644
>--- a/bfd/archures.c
>+++ b/bfd/archures.c
>@@ -505,14 +505,15 @@ DESCRIPTION
> .  bfd_arch_xtensa,    {* Tensilica's Xtensa cores.  *}
> .#define bfd_mach_xtensa	1
> .  bfd_arch_z80,
>-.#define bfd_mach_gbz80         0 {* GameBoy Z80 (reduced instruction set) *}
>-.#define bfd_mach_z80strict	1 {* Z80 without undocumented opcodes.  *}
>-.#define bfd_mach_z180          2 {* Z180: successor with additional instructions, but without halves of ix and iy *}
>-.#define bfd_mach_z80		3 {* Z80 with ixl, ixh, iyl, and iyh.  *}
>-.#define bfd_mach_ez80_z80      4 {* eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode *}
>-.#define bfd_mach_ez80_adl      5 {* eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode *}
>-.#define bfd_mach_z80full	7 {* Z80 with all undocumented instructions.  *}
>-.#define bfd_mach_r800		11 {* R800: successor with multiplication.  *}
>+.#define bfd_mach_z80strict	1 {* Zilog Z80 without undocumented opcodes.  *}
>+.#define bfd_mach_z180		2 {* Zilog Z180: successor with additional instructions, but without halves of ix and iy *}
>+.#define bfd_mach_z80		3 {* Zilog Z80 with ixl, ixh, iyl, and iyh.  *}
>+.#define bfd_mach_ez80_z80	4 {* Zilog eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode *}
>+.#define bfd_mach_ez80_adl	5 {* Zilog eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode *}
>+.#define bfd_mach_z80n		6 {* Z80N *}
>+.#define bfd_mach_z80full	7 {* Zilog Z80 with all undocumented instructions.  *}
>+.#define bfd_mach_gbz80		8 {* GameBoy Z80 (reduced instruction set) *}
>+.#define bfd_mach_r800		11 {* Ascii R800: successor with multiplication.  *}
> .  bfd_arch_lm32,      {* Lattice Mico32.  *}
> .#define bfd_mach_lm32		1
> .  bfd_arch_microblaze,{* Xilinx MicroBlaze.  *}
>diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
>index b9143d3593..ce93dd4930 100644
>--- a/bfd/bfd-in2.h
>+++ b/bfd/bfd-in2.h
>@@ -1888,14 +1888,15 @@ enum bfd_architecture
>   bfd_arch_xtensa,    /* Tensilica's Xtensa cores.  */
> #define bfd_mach_xtensa        1
>   bfd_arch_z80,
>-#define bfd_mach_z80strict     1 /* Z80 without undocumented opcodes.  */
>-#define bfd_mach_z180          2 /* Z180: successor with additional instructions, but without halves of ix and iy */
>-#define bfd_mach_z80           3 /* Z80 with ixl, ixh, iyl, and iyh.  */
>-#define bfd_mach_ez80_z80      4 /* eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode */
>-#define bfd_mach_ez80_adl      5 /* eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode */
>-#define bfd_mach_z80full       7 /* Z80 with all undocumented instructions.  */
>+#define bfd_mach_z80strict     1 /* Zilog Z80 without undocumented opcodes.  */
>+#define bfd_mach_z180          2 /* Zilog Z180: successor with additional instructions, but without halves of ix and iy */
>+#define bfd_mach_z80           3 /* Zilog Z80 with ixl, ixh, iyl, and iyh.  */
>+#define bfd_mach_ez80_z80      4 /* Zilog eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode */
>+#define bfd_mach_ez80_adl      5 /* Zilog eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode */
>+#define bfd_mach_z80n          6 /* Z80N */
>+#define bfd_mach_z80full       7 /* Zilog Z80 with all undocumented instructions.  */
> #define bfd_mach_gbz80         8 /* GameBoy Z80 (reduced instruction set) */
>-#define bfd_mach_r800          11 /* R800: successor with multiplication.  */
>+#define bfd_mach_r800          11 /*Ascii R800: Z80 successor with multiplication.  */
>   bfd_arch_lm32,      /* Lattice Mico32.  */
> #define bfd_mach_lm32          1
>   bfd_arch_microblaze,/* Xilinx MicroBlaze.  */
>@@ -5292,6 +5293,9 @@ BFD_RELOC_XTENSA_ASM_EXPAND.  */
> /* Highest 16 bits of multibyte (32 or 24 bit) value.  */
>   BFD_RELOC_Z80_WORD1,
> 
>+/* 16 bit word big endian */
>+  BFD_RELOC_Z80_16_BE,
>+
> /* DJNZ offset.  */
>   BFD_RELOC_Z8K_DISP7,
> 
>diff --git a/bfd/coff-z80.c b/bfd/coff-z80.c
>index bb519fd654..8913fb5bf9 100644
>--- a/bfd/coff-z80.c
>+++ b/bfd/coff-z80.c
>@@ -221,6 +221,21 @@ static bfd_howto_type howto_table[] =
>      0,			/* src_mask */
>      0xffff,		/* dst_mask */
>      FALSE),		/* pcrel_offset */
>+
>+  BFD_HOWTO (BFD_RELOC_Z80_16_BE,
>+     R_IMM16BE,		/* type */
>+     0,			/* rightshift */
>+     1,			/* size (0 = byte, 1 = short, 2 = long) */
>+     16,		/* bitsize */
>+     FALSE,		/* pc_relative */
>+     0,			/* bitpos */
>+     complain_overflow_bitfield, /* complain_on_overflow */
>+     0,			/* special_function */
>+     "r_imm16be",	/* name */
>+     FALSE,		/* partial_inplace */
>+     0x0000ffff,	/* src_mask */
>+     0x0000ffff,	/* dst_mask */
>+     FALSE),		/* pcrel_offset */
> };
> 
> #define NUM_HOWTOS ARRAY_SIZE (howto_table)
>@@ -421,6 +436,17 @@ extra_case (bfd *in_abfd,
> 	break;
>       }
> 
>+    case R_IMM16BE:
>+      if (reloc->howto->partial_inplace)
>+	val += (bfd_get_8 ( in_abfd, data+*src_ptr+0) * 0x100 +
>+		bfd_get_8 ( in_abfd, data+*src_ptr+1)) & reloc->howto->src_mask;
>+      
>+      bfd_put_8 (in_abfd, val >> 8, data + *dst_ptr+0);
>+      bfd_put_8 (in_abfd, val, data + *dst_ptr+1);
>+      (*dst_ptr) += 2;
>+      (*src_ptr) += 2;
>+      break;
>+
>     default:
>       abort ();
>     }
>diff --git a/bfd/coffcode.h b/bfd/coffcode.h
>index dec2e9c637..96a7f20d3c 100644
>--- a/bfd/coffcode.h
>+++ b/bfd/coffcode.h
>@@ -2163,6 +2163,7 @@ coff_set_arch_mach_hook (bfd *abfd, void * filehdr)
> 	{
> 	case bfd_mach_z80strict << 12:
> 	case bfd_mach_z80 << 12:
>+	case bfd_mach_z80n << 12:
> 	case bfd_mach_z80full << 12:
> 	case bfd_mach_r800 << 12:
> 	case bfd_mach_gbz80 << 12:
>@@ -2655,6 +2656,7 @@ coff_set_flags (bfd * abfd,
> 	{
> 	case bfd_mach_z80strict:
> 	case bfd_mach_z80:
>+	case bfd_mach_z80n:
> 	case bfd_mach_z80full:
> 	case bfd_mach_r800:
> 	case bfd_mach_gbz80:
>diff --git a/bfd/cpu-z80.c b/bfd/cpu-z80.c
>index 96fcfa3658..76f2ff6977 100644
>--- a/bfd/cpu-z80.c
>+++ b/bfd/cpu-z80.c
>@@ -54,7 +54,8 @@ static const bfd_arch_info_type arch_info_struct[] =
>   N (bfd_mach_r800,	 "r800",       16, FALSE, M(4)),
>   N (bfd_mach_gbz80,	 "gbz80",      16, FALSE, M(5)),
>   N (bfd_mach_z180,	 "z180",       16, FALSE, M(6)),
>-  N (bfd_mach_ez80_z80,	 "ez80-z80",   16, FALSE, M(7)),
>+  N (bfd_mach_z80n,	 "z80n",       16, FALSE, M(7)),
>+  N (bfd_mach_ez80_z80,	 "ez80-z80",   16, FALSE, M(8)),
>   N (bfd_mach_ez80_adl,	 "ez80-adl",   24, FALSE, NULL)
> };
> 
>diff --git a/bfd/elf32-z80.c b/bfd/elf32-z80.c
>index c873a8df19..0574c703d8 100644
>--- a/bfd/elf32-z80.c
>+++ b/bfd/elf32-z80.c
>@@ -44,6 +44,11 @@ typedef struct {
> #define BFD_EMPTY_HOWTO(rt,x) {rt, EMPTY_HOWTO(x)}
> #define BFD_HOWTO(rt,a,b,c,d,e,f,g,h,i,j,k,l,m) {rt, HOWTO(a,b,c,d,e,f,g,h,i,j,k,l,m)}
> 
>+static bfd_reloc_status_type
>+z80_elf_16_be_reloc (bfd *abfd, arelent *reloc_entry, asymbol *symbol,
>+		     void *data, asection *input_section, bfd *output_bfd,
>+		     char **error_message);
>+
> static const
> bfd_howto_type elf_z80_howto_table[] =
> {
>@@ -253,6 +258,22 @@ bfd_howto_type elf_z80_howto_table[] =
> 	 0,			/* src_mask */
> 	 0xffff,		/* dst_mask */
> 	 FALSE),		/* pcrel_offset */
>+
>+  /* An 16 bit big endian absolute relocation */
>+  BFD_HOWTO (BFD_RELOC_Z80_16_BE,
>+	 R_Z80_16_BE,		/* type */
>+	 0,			/* rightshift */
>+	 1,			/* size (0 = byte, 1 = short, 2 = long) */
>+	 16,			/* bitsize */
>+	 FALSE,			/* pc_relative */
>+	 0,			/* bitpos */
>+	 complain_overflow_bitfield,	/* complain_on_overflow */
>+	 z80_elf_16_be_reloc,	/* special_function */
>+	 "r_imm16be",		/* name */
>+	 FALSE,			/* partial_inplace */
>+	 0x00000000,		/* src_mask */
>+	 0x0000ffff,		/* dst_mask */
>+	 FALSE),		/* pcrel_offset */
> };
> 
> static reloc_howto_type *
>@@ -347,6 +368,9 @@ z80_elf_set_mach_from_flags (bfd *abfd)
>     case EF_Z80_MACH_R800:
>       mach = bfd_mach_r800;
>       break;
>+    case EF_Z80_MACH_Z80N:
>+      mach = bfd_mach_z80n;
>+      break;
>     default:
>       mach = bfd_mach_z80;
>       break;
>@@ -364,6 +388,56 @@ z80_is_local_label_name (bfd *        abfd ATTRIBUTE_UNUSED,
>          _bfd_elf_is_local_label_name (abfd, name);
> }
> 
>+static bfd_reloc_status_type
>+z80_elf_16_be_reloc (bfd *abfd,
>+		     arelent *reloc_entry,
>+		     asymbol *symbol,
>+		     void *data,
>+		     asection *input_section,
>+		     bfd *output_bfd,
>+		     char **error_message)
>+{
>+  bfd_vma val;
>+  long x;
>+  bfd_size_type octets = (reloc_entry->address
>+                          * OCTETS_PER_BYTE (abfd, input_section));
>+
>+  /* If this is a relocatable link (output_bfd test tells us), just
>+     call the generic function.  Any adjustment will be done at final
>+     link time.  */
>+  if (output_bfd != NULL)
>+    return bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data,
>+                                  input_section, output_bfd, error_message);
>+
>+  /*if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
>+    return bfd_reloc_outofrange;*/
>+
>+  /* Get symbol value.  */
>+  val = 0;
>+  if (!bfd_is_com_section (symbol->section))
>+    val = symbol->value;
>+  val += symbol->section->output_offset + input_section->output_offset;
>+  if (symbol->section->output_section)
>+    val += symbol->section->output_section->vma;
>+
>+  val += reloc_entry->addend;
>+  if (reloc_entry->howto->partial_inplace)
>+    {
>+      x = bfd_get_8 (abfd, (bfd_byte *) data + octets + 0) * 0x100;
>+      x += bfd_get_8 (abfd, (bfd_byte *) data + octets + 1);
>+      x &= ~reloc_entry->howto->src_mask;
>+    }
>+  else
>+    x = 0;
>+
>+  x |= val & reloc_entry->howto->dst_mask;
>+  if (x < -0x8000 || x >= 0x10000)
>+    return bfd_reloc_outofrange;
>+
>+  bfd_put_8 (abfd, x >> 8, (bfd_byte *) data + octets + 0);
>+  bfd_put_8 (abfd, x >> 0, (bfd_byte *) data + octets + 1);
>+  return bfd_reloc_ok;
>+}
> 
> #define ELF_ARCH		bfd_arch_z80
> #define ELF_MACHINE_CODE	EM_Z80
>diff --git a/bfd/libbfd.h b/bfd/libbfd.h
>index d97d4e57a7..a3684a94cc 100644
>--- a/bfd/libbfd.h
>+++ b/bfd/libbfd.h
>@@ -2875,6 +2875,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
>   "BFD_RELOC_Z80_BYTE3",
>   "BFD_RELOC_Z80_WORD0",
>   "BFD_RELOC_Z80_WORD1",
>+  "BFD_RELOC_Z80_16_BE",
>   "BFD_RELOC_Z8K_DISP7",
>   "BFD_RELOC_Z8K_CALLR",
>   "BFD_RELOC_Z8K_IMM4L",
>diff --git a/bfd/reloc.c b/bfd/reloc.c
>index 33cd67150c..dab7d17b47 100644
>--- a/bfd/reloc.c
>+++ b/bfd/reloc.c
>@@ -6697,6 +6697,10 @@ ENUM
>   BFD_RELOC_Z80_WORD1
> ENUMDOC
>   Highest 16 bits of multibyte (32 or 24 bit) value.
>+ENUM
>+  BFD_RELOC_Z80_16_BE
>+ENUMDOC
>+  Like BFD_RELOC_16 but big-endian.
> 
> ENUM
>   BFD_RELOC_Z8K_DISP7
>diff --git a/binutils/readelf.c b/binutils/readelf.c
>index eabb70fac9..5b87ec362a 100644
>--- a/binutils/readelf.c
>+++ b/binutils/readelf.c
>@@ -3767,6 +3767,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
> 	    case EF_Z80_MACH_EZ80_Z80: strcat (buf, ", EZ80"); break;
> 	    case EF_Z80_MACH_EZ80_ADL: strcat (buf, ", EZ80, ADL"); break;
> 	    case EF_Z80_MACH_GBZ80: strcat (buf, ", GBZ80"); break;
>+	    case EF_Z80_MACH_Z80N: strcat (buf, ", Z80N"); break;
> 	    default:
> 	      strcat (buf, _(", unknown")); break;
> 	    }
>diff --git a/gas/config/tc-z80.c b/gas/config/tc-z80.c
>index 02aa2367d2..b36f57ef94 100644
>--- a/gas/config/tc-z80.c
>+++ b/gas/config/tc-z80.c
>@@ -44,6 +44,7 @@ enum options
>   OPTION_MACH_EZ80_Z80,
>   OPTION_MACH_EZ80_ADL,
>   OPTION_MACH_GBZ80,
>+  OPTION_MACH_Z80N,
>   OPTION_MACH_INST,
>   OPTION_MACH_NO_INST,
>   OPTION_MACH_IUD,
>@@ -64,6 +65,7 @@ enum options
> #define INS_GBZ80    (1 << 2)
> #define INS_Z180     (1 << 3)
> #define INS_EZ80     (1 << 4)
>+#define INS_Z80N     (1 << 5)
> #define INS_MARCH_MASK 0xffff
> 
> #define INS_IDX_HALF (1 << 16)
>@@ -73,7 +75,7 @@ enum options
> #define INS_ROT_II_LD (1 << 20)  /* instructions like SLA (ii+d),r; which is: LD r,(ii+d); SLA r; LD (ii+d),r */
> #define INS_TUNE_MASK 0xffff0000
> 
>-#define INS_NOT_GBZ80 (INS_Z80 | INS_Z180 | INS_R800 | INS_EZ80)
>+#define INS_NOT_GBZ80 (INS_Z80 | INS_Z180 | INS_R800 | INS_EZ80 | INS_Z80N)
> 
> #define INS_ALL 0
> #define INS_UNDOC (INS_IDX_HALF | INS_IN_F_C)
>@@ -87,6 +89,7 @@ struct option md_longopts[] =
>   { "ez80",      no_argument, NULL, OPTION_MACH_EZ80_Z80},
>   { "ez80-adl",  no_argument, NULL, OPTION_MACH_EZ80_ADL},
>   { "gbz80",     no_argument, NULL, OPTION_MACH_GBZ80},
>+  { "z80n",      no_argument, NULL, OPTION_MACH_Z80N},
>   { "fp-s",      required_argument, NULL, OPTION_FP_SINGLE_FORMAT},
>   { "fp-d",      required_argument, NULL, OPTION_FP_DOUBLE_FORMAT},
>   { "strict",    no_argument, NULL, OPTION_MACH_FUD},
>@@ -245,7 +248,7 @@ md_parse_option (int c, const char* arg)
>       ins_err = (ins_err & INS_MARCH_MASK) | (~INS_Z80 & INS_MARCH_MASK);
>       break;
>     case OPTION_MACH_R800:
>-      ins_ok = INS_R800 | INS_IDX_HALF;
>+      ins_ok = INS_R800 | INS_IDX_HALF | INS_IN_F_C;
>       ins_err = INS_UNPORT;
>       break;
>     case OPTION_MACH_Z180:
>@@ -253,12 +256,12 @@ md_parse_option (int c, const char* arg)
>       ins_err = INS_UNDOC | INS_UNPORT;
>       break;
>     case OPTION_MACH_EZ80_Z80:
>-      ins_ok = INS_EZ80;
>+      ins_ok = INS_EZ80 | INS_IDX_HALF;
>       ins_err = (INS_UNDOC | INS_UNPORT) & ~INS_IDX_HALF;
>       cpu_mode = 0;
>       break;
>     case OPTION_MACH_EZ80_ADL:
>-      ins_ok = INS_EZ80;
>+      ins_ok = INS_EZ80 | INS_IDX_HALF;
>       ins_err = (INS_UNDOC | INS_UNPORT) & ~INS_IDX_HALF;
>       cpu_mode = 1;
>       break;
>@@ -266,6 +269,10 @@ md_parse_option (int c, const char* arg)
>       ins_ok = INS_GBZ80;
>       ins_err = INS_UNDOC | INS_UNPORT;
>       break;
>+    case OPTION_MACH_Z80N:
>+      ins_ok = INS_Z80N | INS_UNPORT | INS_UNDOC;
>+      ins_err = 0;
>+      break;
>     case OPTION_FP_SINGLE_FORMAT:
>       str_to_float = get_str_to_float (arg);
>       break;
>@@ -327,12 +334,13 @@ md_show_usage (FILE * f)
> {
>   fprintf (f, "\n\
> CPU model options:\n\
>-  -z80\t\t\t  assemble for Z80\n\
>-  -r800\t\t\t  assemble for R800\n\
>-  -z180\t\t\t  assemble for Z180\n\
>-  -ez80\t\t\t  assemble for eZ80 in Z80 mode by default\n\
>-  -ez80-adl\t\t  assemble for eZ80 in ADL mode by default\n\
>+  -z80\t\t\t  assemble for Zilog Z80\n\
>+  -r800\t\t\t  assemble for Ascii R800\n\
>+  -z180\t\t\t  assemble for Zilog Z180\n\
>+  -ez80\t\t\t  assemble for Zilog eZ80 in Z80 mode by default\n\
>+  -ez80-adl\t\t  assemble for Zilog eZ80 in ADL mode by default\n\
>   -gbz80\t\t  assemble for GameBoy Z80\n\
>+  -z80n\t\t\t  assemble for Z80N\n\
> \n\
> Compatibility options:\n\
>   -local-prefix=TEXT\t  treat labels prefixed by TEXT as local\n\
>@@ -510,6 +518,9 @@ z80_md_end (void)
>     case INS_EZ80:
>       mach_type = cpu_mode ? bfd_mach_ez80_adl : bfd_mach_ez80_z80;
>       break;
>+    case INS_Z80N:
>+      mach_type = bfd_mach_z80n;
>+      break;
>     default:
>       mach_type = 0;
>     }
>@@ -539,6 +550,9 @@ z80_elf_final_processing (void)
>     case INS_EZ80:
>       elf_flags = cpu_mode ? EF_Z80_MACH_EZ80_ADL : EF_Z80_MACH_EZ80_Z80;
>       break;
>+    case INS_Z80N:
>+      elf_flags = EF_Z80_MACH_Z80N;
>+      break;
>     default:
>       elf_flags = 0;
>     }
>@@ -1351,16 +1365,42 @@ emit_sub (char prefix, char opcode, const char *args)
>   if (!(ins_ok & INS_GBZ80))
>     return emit_s (prefix, opcode, args);
>   p = parse_exp (args, & arg_s);
>-  if (*p != ',' || arg_s.X_md != 0 || arg_s.X_op != O_register || arg_s.X_add_number != REG_A)
>+  if (*p++ != ',')
>+    {
>+      error (_("bad instruction syntax"));
>+      return p;
>+    }
>+
>+  if (arg_s.X_md != 0 || arg_s.X_op != O_register || arg_s.X_add_number != REG_A)
>     ill_op ();
> 
>-  ++p;
>   p = parse_exp (p, & arg_s);
> 
>   emit_sx (prefix, opcode, & arg_s);
>   return p;
> }
> 
>+static const char *
>+emit_swap (char prefix, char opcode, const char *args)
>+{
>+  expressionS reg;
>+  const char *p;
>+  char *q;
>+
>+  if (!(ins_ok & INS_Z80N))
>+    return emit_mr (prefix, opcode, args);
>+
>+  /* check for alias swap a for swapnib of Z80N */
>+  p = parse_exp (args, &reg);
>+  if (reg.X_md != 0 || reg.X_op != O_register || reg.X_add_number != REG_A)
>+    ill_op ();
>+
>+  q = frag_more (2);
>+  *q++ = 0xED;
>+  *q = 0x23;
>+  return p;
>+}
>+
> static const char *
> emit_call (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
> {
>@@ -1447,6 +1487,12 @@ emit_jp (char prefix, char opcode, const char * args)
> 	    *q++ = (rnum & R_IX) ? 0xDD : 0xFD;
> 	  *q = prefix;
> 	}
>+      else if (addr.X_op == O_register && rnum == REG_C && (ins_ok & INS_Z80N))
>+	{
>+	  q = frag_more (2);
>+	  *q++ = 0xED;
>+	  *q = 0x98;
>+	}
>       else
> 	ill_op ();
>     }
>@@ -1517,6 +1563,31 @@ emit_pop (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
>   return p;
> }
> 
>+static const char *
>+emit_push (char prefix, char opcode, const char * args)
>+{
>+  expressionS arg;
>+  const char *p;
>+  char *q;
>+
>+  p = parse_exp (args, & arg);
>+  if (arg.X_op == O_register)
>+    return emit_pop (prefix, opcode, args);
>+
>+  if (arg.X_md || arg.X_op == O_md1 || !(ins_ok & INS_Z80N))
>+    ill_op ();
>+
>+  q = frag_more (2);
>+  *q++ = 0xED;
>+  *q = 0x8A;
>+
>+  q = frag_more (2);
>+  fix_new_exp (frag_now, q - frag_now->fr_literal, 2, &arg, FALSE,
>+               BFD_RELOC_Z80_16_BE);
>+
>+  return p;
>+}
>+
> static const char *
> emit_retcc (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
> {
>@@ -1593,7 +1664,7 @@ emit_add (char prefix, char opcode, const char * args)
>   if ((term.X_md) || (term.X_op != O_register))
>     ill_op ();
>   else
>-    switch (term.X_add_number & ~R_INDEX)
>+    switch (term.X_add_number)
>       {
>       case REG_A:
> 	p = emit_s (0, prefix, p);
>@@ -1606,14 +1677,25 @@ emit_add (char prefix, char opcode, const char * args)
> 	*q = 0xE8;
> 	emit_byte (&term, BFD_RELOC_Z80_DISP8);
> 	break;
>+      case REG_BC:
>+      case REG_DE:
>+	if (!(ins_ok & INS_Z80N))
>+	  {
>+	    ill_op ();
>+	    break;
>+	  }
>+	/* Fall through.  */
>       case REG_HL:
>+      case REG_IX:
>+      case REG_IY:
> 	lhs = term.X_add_number;
> 	p = parse_exp (p, &term);
>-	if ((!term.X_md) && (term.X_op == O_register))
>+	rhs = term.X_add_number;
>+	if (term.X_md != 0 || term.X_op == O_md1)
>+	  ill_op ();
>+	else if ((term.X_op == O_register) && (rhs & R_ARITH) && (rhs == lhs || (rhs & ~R_INDEX) != REG_HL))
> 	  {
>-	    rhs = term.X_add_number;
>-	    if ((rhs & R_ARITH)
>-		&& ((rhs == lhs) || ((rhs & ~R_INDEX) != REG_HL)))
>+	    if (1)
> 	      {
> 		q = frag_more ((lhs & R_INDEX) ? 2 : 1);
> 		if (lhs & R_INDEX)
>@@ -1622,6 +1704,24 @@ emit_add (char prefix, char opcode, const char * args)
> 		break;
> 	      }
> 	  }
>+	else if (!(lhs & R_INDEX) && (ins_ok & INS_Z80N))
>+	  {
>+	    if (term.X_op == O_register && rhs == REG_A)
>+	      { /* ADD BC/DE/HL,A */
>+		q = frag_more (2);
>+		*q++ = 0xED;
>+		*q = 0x33 - (lhs & 3);
>+		break;
>+	      }
>+	    else if (term.X_op != O_register && term.X_op != O_md1)
>+	      { /* ADD BC/DE/HL,nn */
>+		q = frag_more (2);
>+		*q++ = 0xED;
>+		*q = 0x36 - (lhs & 3);
>+		emit_word (&term);
>+		break;
>+	      }
>+	  }
> 	/* Fall through.  */
>       default:
> 	ill_op ();
>@@ -1658,6 +1758,27 @@ emit_bit (char prefix, char opcode, const char * args)
>   return p;
> }
> 
>+/* BSLA DE,B; BSRA DE,B; BSRL DE,B; BSRF DE,B; BRLC DE,B (Z80N only) */
>+static const char *
>+emit_bshft (char prefix, char opcode, const char * args)
>+{
>+  expressionS r1, r2;
>+  const char *p;
>+  char *q;
>+
>+  p = parse_exp (args, & r1);
>+  if (*p++ != ',')
>+    error (_("bad instruction syntax"));
>+  p = parse_exp (p, & r2);
>+  if (r1.X_md || r1.X_op != O_register || r1.X_add_number != REG_DE ||
>+      r2.X_md || r2.X_op != O_register || r2.X_add_number != REG_B)
>+    ill_op ();
>+  q = frag_more (2);
>+  *q++ = prefix;
>+  *q = opcode;
>+  return p;
>+}
>+
> static const char *
> emit_jpcc (char prefix, char opcode, const char * args)
> {
>@@ -1756,13 +1877,21 @@ emit_in (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED,
>   char *q;
> 
>   p = parse_exp (args, &reg);
>-  if (*p++ != ',')
>+  if (reg.X_md && reg.X_op == O_register && reg.X_add_number == REG_C)
>+    { /* permit instruction in (c) as alias for in f,(c) */
>+      port = reg;
>+      reg.X_md = 0;
>+      reg.X_add_number = REG_F;
>+    }
>+  else
>     {
>-      error (_("bad instruction syntax"));
>-      return p;
>+      if (*p++ != ',')
>+	{
>+	  error (_("bad instruction syntax"));
>+	  return p;
>+	}
>+      p = parse_exp (p, &port);
>     }
>-
>-  p = parse_exp (p, &port);
>   if (reg.X_md == 0
>       && reg.X_op == O_register
>       && (reg.X_add_number <= 7 || reg.X_add_number == REG_F)
>@@ -2750,10 +2879,73 @@ emit_mlt (char prefix, char opcode, const char * args)
>   if (arg.X_md != 0 || arg.X_op != O_register || !(arg.X_add_number & R_ARITH))
>     ill_op ();
> 
>+  q = frag_more (2);
>+  if (ins_ok & INS_Z80N)
>+    {
>+      if (arg.X_add_number != REG_DE)
>+	ill_op ();
>+      *q++ = 0xED;
>+      *q = 0x30;
>+    }
>+  else
>+    {
>+      *q++ = prefix;
>+      *q = opcode | ((arg.X_add_number & 3) << 4);
>+    }
>+
>+  return p;
>+}
>+
>+/* MUL D,E (Z80N only) */
>+static const char *
>+emit_mul (char prefix, char opcode, const char * args)
>+{
>+  expressionS r1, r2;
>+  const char *p;
>+  char *q;
>+
>+  p = parse_exp (args, & r1);
>+  if (*p++ != ',')
>+    error (_("bad instruction syntax"));
>+  p = parse_exp (p, & r2);
>+
>+  if (r1.X_md != 0 || r1.X_op != O_register || r1.X_add_number != REG_D ||
>+      r2.X_md != 0 || r2.X_op != O_register || r2.X_add_number != REG_E)
>+    ill_op ();
>+
>   q = frag_more (2);
>   *q++ = prefix;
>-  *q = opcode | ((arg.X_add_number & 3) << 4);
>+  *q = opcode;
>+
>+  return p;
>+}
> 
>+static const char *
>+emit_nextreg (char prefix, char opcode ATTRIBUTE_UNUSED, const char * args)
>+{
>+  expressionS rr, nn;
>+  const char *p;
>+  char *q;
>+
>+  p = parse_exp (args, & rr);
>+  if (*p++ != ',')
>+    error (_("bad instruction syntax"));
>+  p = parse_exp (p, & nn);
>+  if (rr.X_md != 0 || rr.X_op == O_register || rr.X_op == O_md1 ||
>+      nn.X_md != 0 || nn.X_op == O_md1)
>+    ill_op ();
>+  q = frag_more (2);
>+  *q++ = prefix;
>+  emit_byte (&rr, BFD_RELOC_8);
>+  if (nn.X_op == O_register && nn.X_add_number == REG_A)
>+    *q = 0x92;
>+  else if (nn.X_op != O_register)
>+    {
>+      *q = 0x91;
>+      emit_byte (&nn, BFD_RELOC_8);
>+    }
>+  else
>+    ill_op ();
>   return p;
> }
> 
>@@ -2834,15 +3026,23 @@ emit_tst (char prefix, char opcode, const char *args)
>       if (arg_s.X_md)
>         ill_op ();
>       q = frag_more (2);
>-      *q++ = prefix;
>-      *q = opcode | 0x60;
>+      if (ins_ok & INS_Z80N)
>+	{
>+	  *q++ = 0xED;
>+	  *q = 0x27;
>+	}
>+      else
>+	{
>+	  *q++ = prefix;
>+	  *q = opcode | 0x60;
>+	}
>       emit_byte (& arg_s, BFD_RELOC_8);
>     }
>   return p;
> }
> 
> static const char *
>-emit_tstio (char prefix, char opcode, const char *args)
>+emit_insn_n (char prefix, char opcode, const char *args)
> {
>   expressionS arg;
>   const char *p;
>@@ -3181,6 +3381,7 @@ const pseudo_typeS md_pseudo_table[] =
>   { ".set", s_set, 0},
>   { ".z180", set_inss, INS_Z180},
>   { ".z80", set_inss, INS_Z80},
>+  { ".z80n", set_inss, INS_Z80N},
>   { "db" , emit_data, 1},
>   { "d24", z80_cons, 3},
>   { "d32", z80_cons, 4},
>@@ -3203,6 +3404,11 @@ static table_t instab[] =
>   { "add",  0x80, 0x09, emit_add,  INS_ALL },
>   { "and",  0x00, 0xA0, emit_s,    INS_ALL },
>   { "bit",  0xCB, 0x40, emit_bit,  INS_ALL },
>+  { "brlc", 0xED, 0x2C, emit_bshft,INS_Z80N },
>+  { "bsla", 0xED, 0x28, emit_bshft,INS_Z80N },
>+  { "bsra", 0xED, 0x29, emit_bshft,INS_Z80N },
>+  { "bsrf", 0xED, 0x2B, emit_bshft,INS_Z80N },
>+  { "bsrl", 0xED, 0x2A, emit_bshft,INS_Z80N },
>   { "call", 0xCD, 0xC4, emit_jpcc, INS_ALL },
>   { "ccf",  0x00, 0x3F, emit_insn, INS_ALL },
>   { "cp",   0x00, 0xB8, emit_s,    INS_ALL },
>@@ -3242,15 +3448,24 @@ static table_t instab[] =
>   { "ld",   0x00, 0x00, emit_ld,   INS_ALL },
>   { "ldd",  0xED, 0xA8, emit_lddldi,INS_ALL }, /* GBZ80 has special meaning */
>   { "lddr", 0xED, 0xB8, emit_insn, INS_NOT_GBZ80 },
>+  { "lddrx",0xED, 0xBC, emit_insn, INS_Z80N },
>+  { "lddx", 0xED, 0xAC, emit_insn, INS_Z80N },
>   { "ldh",  0xE0, 0x00, emit_ldh,  INS_GBZ80 },
>   { "ldhl", 0x00, 0xF8, emit_ldhl, INS_GBZ80 },
>   { "ldi",  0xED, 0xA0, emit_lddldi,INS_ALL }, /* GBZ80 has special meaning */
>   { "ldir", 0xED, 0xB0, emit_insn, INS_NOT_GBZ80 },
>+  { "ldirx",0xED, 0xB4, emit_insn, INS_Z80N },
>+  { "ldix", 0xED, 0xA4, emit_insn, INS_Z80N },
>+  { "ldpirx",0xED,0xB7, emit_insn, INS_Z80N },
>+  { "ldws", 0xED, 0xA5, emit_insn, INS_Z80N },
>   { "lea",  0xED, 0x02, emit_lea,  INS_EZ80 },
>-  { "mlt",  0xED, 0x4C, emit_mlt,  INS_Z180|INS_EZ80 },
>+  { "mirror",0xED,0x24, emit_insn, INS_Z80N },
>+  { "mlt",  0xED, 0x4C, emit_mlt,  INS_Z180|INS_EZ80|INS_Z80N },
>+  { "mul",  0xED, 0x30, emit_mul,  INS_Z80N },
>   { "mulub",0xED, 0xC5, emit_mulub,INS_R800 },
>   { "muluw",0xED, 0xC3, emit_muluw,INS_R800 },
>-  { "neg",  0xed, 0x44, emit_insn, INS_NOT_GBZ80 },
>+  { "neg",  0xED, 0x44, emit_insn, INS_NOT_GBZ80 },
>+  { "nextreg",0xED,0x91,emit_nextreg,INS_Z80N },
>   { "nop",  0x00, 0x00, emit_insn, INS_ALL },
>   { "or",   0x00, 0xB0, emit_s,    INS_ALL },
>   { "otd2r",0xED, 0xBC, emit_insn, INS_EZ80 },
>@@ -3269,9 +3484,12 @@ static table_t instab[] =
>   { "outd2",0xED, 0xAC, emit_insn, INS_EZ80 },
>   { "outi", 0xED, 0xA3, emit_insn, INS_NOT_GBZ80 },
>   { "outi2",0xED, 0xA4, emit_insn, INS_EZ80 },
>+  { "outinb",0xED,0x90, emit_insn, INS_Z80N },
>   { "pea",  0xED, 0x65, emit_pea,  INS_EZ80 },
>+  { "pixelad",0xED,0x94,emit_insn, INS_Z80N },
>+  { "pixeldn",0xED,0x93,emit_insn, INS_Z80N },
>   { "pop",  0x00, 0xC1, emit_pop,  INS_ALL },
>-  { "push", 0x00, 0xC5, emit_pop,  INS_ALL },
>+  { "push", 0x00, 0xC5, emit_push, INS_ALL },
>   { "res",  0xCB, 0x80, emit_bit,  INS_ALL },
>   { "ret",  0xC9, 0xC0, emit_retcc,INS_ALL },
>   { "reti", 0xED, 0x4D, emit_reti, INS_ALL }, /*GBZ80 has its own opcode for it*/
>@@ -3291,6 +3509,8 @@ static table_t instab[] =
>   { "sbc",  0x98, 0x42, emit_adc,  INS_ALL },
>   { "scf",  0x00, 0x37, emit_insn, INS_ALL },
>   { "set",  0xCB, 0xC0, emit_bit,  INS_ALL },
>+  { "setae",0xED, 0x95, emit_insn, INS_Z80N },
>+  { "sl1",  0xCB, 0x30, emit_mr,   INS_SLI },
>   { "sla",  0xCB, 0x20, emit_mr,   INS_ALL },
>   { "sli",  0xCB, 0x30, emit_mr,   INS_SLI },
>   { "sll",  0xCB, 0x30, emit_mr,   INS_SLI },
>@@ -3300,9 +3520,11 @@ static table_t instab[] =
>   { "stmix",0xED, 0x7D, emit_insn, INS_EZ80 },
>   { "stop", 0x00, 0x10, emit_insn, INS_GBZ80 },
>   { "sub",  0x00, 0x90, emit_sub,  INS_ALL },
>-  { "swap", 0xCB, 0x30, emit_mr,   INS_GBZ80 },
>-  { "tst",  0xED, 0x04, emit_tst,  INS_Z180|INS_EZ80 },
>-  { "tstio",0xED, 0x74, emit_tstio,INS_Z180|INS_EZ80 },
>+  { "swap", 0xCB, 0x30, emit_swap, INS_GBZ80|INS_Z80N },
>+  { "swapnib",0xED,0x23,emit_insn, INS_Z80N },
>+  { "test", 0xED, 0x27, emit_insn_n, INS_Z80N },
>+  { "tst",  0xED, 0x04, emit_tst,  INS_Z180|INS_EZ80|INS_Z80N },
>+  { "tstio",0xED, 0x74, emit_insn_n,INS_Z180|INS_EZ80 },
>   { "xor",  0x00, 0xA8, emit_s,    INS_ALL },
> } ;
> 
>@@ -3476,6 +3698,13 @@ md_apply_fix (fixS * fixP, valueT* valP, segT seg ATTRIBUTE_UNUSED)
> 	fixP->fx_done = 1;
>       break;
> 
>+    case BFD_RELOC_Z80_16_BE: /* Z80N PUSH nn instruction produce this.  */
>+      *p_lit++ = val >> 8;
>+      *p_lit++ = val;
>+      if (fixP->fx_addsy == NULL)
>+	fixP->fx_done = 1;
>+      break;
>+
>     default:
>       printf (_("md_apply_fix: unknown r_type 0x%x\n"), fixP->fx_r_type);
>       abort ();
>diff --git a/gas/config/tc-z80.h b/gas/config/tc-z80.h
>index 5ce638d459..71a5895e19 100644
>--- a/gas/config/tc-z80.h
>+++ b/gas/config/tc-z80.h
>@@ -29,7 +29,7 @@
> #endif
> #define BFD_ARCH      TARGET_ARCH
> #define COFF_MAGIC    0x5A80
>-#define TARGET_MACH   0
>+//#define TARGET_MACH   0
> #define TARGET_BYTES_BIG_ENDIAN  0
> 
> /* If you define this macro, GAS will warn about the
>diff --git a/gas/doc/c-z80.texi b/gas/doc/c-z80.texi
>index d6b4d3f443..e768e38c7a 100644
>--- a/gas/doc/c-z80.texi
>+++ b/gas/doc/c-z80.texi
>@@ -31,19 +31,19 @@
> @table @gcctabopt
> @cindex @code{-z80} command-line option, Z80
> @item -z80
>-Produce code for the Z80 processor. By default accepted undocumented
>-operations with halves of index registers (@code{IXL}, @code{IXH}, @code{IYL}, @code{IYH}) and
>-instuction @code{IN F,(C)}. Other useful undocumented instructions produces
>-warnings. Undocumented instructions may not work on some CPUs, use
>-them on your own risk.
>+Produce code for the Zilog Z80 processor. By default accepted undocumented
>+operations with halves of index registers (@code{IXL}, @code{IXH}, @code{IYL},
>+@code{IYH}) and instuction @code{IN F,(C)}. Other useful undocumented
>+instructions produces warnings. Undocumented instructions may not work on some
>+CPUs, use them on your own risk.
> 
> @cindex @code{-r800} command-line option, Z80
> @item -r800
>-Produce code for the R800 processor.
>+Produce code for the Ascii R800 processor.
> 
> @cindex @code{-z180} command-line option, Z80
> @item -z180
>-Produce code for the Z180 processor.
>+Produce code for the Zilog Z180 processor.
> 
> @cindex @code{-ez80} command-line option, Z80
> @item -ez80
>@@ -57,6 +57,10 @@ Produce code for the eZ80 processor in ADL memory mode by default.
> @item -gbz80
> Produce code for the GameBoy Z80 processor.
> 
>+@cindex @code{-z80n} command-line option, Z80
>+@item -z80n
>+Produce code for the Z80N processor.
>+
> @cindex @code{-local-prefix} command-line option, Z80
> @item  -local-prefix=@var{prefix}
> Mark all labels with specified prefix as local. But such label can be
>diff --git a/gas/testsuite/gas/z80/z80.exp b/gas/testsuite/gas/z80/z80.exp
>index e4209d1fd3..31f61133b2 100644
>--- a/gas/testsuite/gas/z80/z80.exp
>+++ b/gas/testsuite/gas/z80/z80.exp
>@@ -94,6 +94,10 @@ if [istarget z80-*-*] then {
>     run_dump_test "ez80_pref_dis"
> #test for GBZ80 instruction set
>     run_dump_test "gbz80_all"
>+#test for Z80N instruction set
>+    run_dump_test "z80n_all"
>+#test for Z80N push nn relocation test
>+    run_dump_test "z80n_reloc"
> # test for SDCC compatibility mode
>     run_dump_test "sdcc"
> # test for colonless labels
>diff --git a/gas/testsuite/gas/z80/z80n_all.d b/gas/testsuite/gas/z80/z80n_all.d
>new file mode 100644
>index 0000000000..3412905f98
>--- /dev/null
>+++ b/gas/testsuite/gas/z80/z80n_all.d
>@@ -0,0 +1,1208 @@
>+#as: -z80n
>+#objdump: -d
>+
>+.*:[     ]+file format (coff|elf32)\-z80
>+
>+
>+Disassembly of section \.text:
>+
>+00000000 <\.text>:
>+[   ]+0:[ 	]+8e[          	]+adc a,$hl$
>+[   ]+1:[ 	]+dd 8e 09[    	]+adc a,$ix\+9$
>+[   ]+4:[ 	]+fd 8e 09[    	]+adc a,$iy\+9$
>+[   ]+7:[ 	]+ce 03[       	]+adc a,0x03
>+[   ]+9:[ 	]+8f[          	]+adc a,a
>+[   ]+a:[ 	]+88[          	]+adc a,b
>+[   ]+b:[ 	]+89[          	]+adc a,c
>+[   ]+c:[ 	]+8a[          	]+adc a,d
>+[   ]+d:[ 	]+8b[          	]+adc a,e
>+[   ]+e:[ 	]+8c[          	]+adc a,h
>+[   ]+f:[ 	]+8d[          	]+adc a,l
>+[  ]+10:[ 	]+ed 4a[       	]+adc hl,bc
>+[  ]+12:[ 	]+ed 5a[       	]+adc hl,de
>+[  ]+14:[ 	]+ed 6a[       	]+adc hl,hl
>+[  ]+16:[ 	]+ed 7a[       	]+adc hl,sp
>+[  ]+18:[ 	]+86[          	]+add a,$hl$
>+[  ]+19:[ 	]+dd 86 09[    	]+add a,$ix\+9$
>+[  ]+1c:[ 	]+fd 86 09[    	]+add a,$iy\+9$
>+[  ]+1f:[ 	]+c6 03[       	]+add a,0x03
>+[  ]+21:[ 	]+87[          	]+add a,a
>+[  ]+22:[ 	]+80[          	]+add a,b
>+[  ]+23:[ 	]+81[          	]+add a,c
>+[  ]+24:[ 	]+82[          	]+add a,d
>+[  ]+25:[ 	]+83[          	]+add a,e
>+[  ]+26:[ 	]+84[          	]+add a,h
>+[  ]+27:[ 	]+85[          	]+add a,l
>+[  ]+28:[ 	]+09[          	]+add hl,bc
>+[  ]+29:[ 	]+19[          	]+add hl,de
>+[  ]+2a:[ 	]+29[          	]+add hl,hl
>+[  ]+2b:[ 	]+39[          	]+add hl,sp
>+[  ]+2c:[ 	]+dd 09[       	]+add ix,bc
>+[  ]+2e:[ 	]+dd 19[       	]+add ix,de
>+[  ]+30:[ 	]+dd 29[       	]+add ix,ix
>+[  ]+32:[ 	]+dd 39[       	]+add ix,sp
>+[  ]+34:[ 	]+fd 09[       	]+add iy,bc
>+[  ]+36:[ 	]+fd 19[       	]+add iy,de
>+[  ]+38:[ 	]+fd 29[       	]+add iy,iy
>+[  ]+3a:[ 	]+fd 39[       	]+add iy,sp
>+[  ]+3c:[ 	]+a6[          	]+and $hl$
>+[  ]+3d:[ 	]+dd a6 09[    	]+and $ix\+9$
>+[  ]+40:[ 	]+fd a6 09[    	]+and $iy\+9$
>+[  ]+43:[ 	]+e6 03[       	]+and 0x03
>+[  ]+45:[ 	]+a7[          	]+and a
>+[  ]+46:[ 	]+a0[          	]+and b
>+[  ]+47:[ 	]+a1[          	]+and c
>+[  ]+48:[ 	]+a2[          	]+and d
>+[  ]+49:[ 	]+a3[          	]+and e
>+[  ]+4a:[ 	]+a4[          	]+and h
>+[  ]+4b:[ 	]+a5[          	]+and l
>+[  ]+4c:[ 	]+cb 46[       	]+bit 0,$hl$
>+[  ]+4e:[ 	]+dd cb 09 46[ 	]+bit 0,$ix\+9$
>+[  ]+52:[ 	]+fd cb 09 46[ 	]+bit 0,$iy\+9$
>+[  ]+56:[ 	]+cb 47[       	]+bit 0,a
>+[  ]+58:[ 	]+cb 40[       	]+bit 0,b
>+[  ]+5a:[ 	]+cb 41[       	]+bit 0,c
>+[  ]+5c:[ 	]+cb 42[       	]+bit 0,d
>+[  ]+5e:[ 	]+cb 43[       	]+bit 0,e
>+[  ]+60:[ 	]+cb 44[       	]+bit 0,h
>+[  ]+62:[ 	]+cb 45[       	]+bit 0,l
>+[  ]+64:[ 	]+cb 4e[       	]+bit 1,$hl$
>+[  ]+66:[ 	]+dd cb 09 4e[ 	]+bit 1,$ix\+9$
>+[  ]+6a:[ 	]+fd cb 09 4e[ 	]+bit 1,$iy\+9$
>+[  ]+6e:[ 	]+cb 4f[       	]+bit 1,a
>+[  ]+70:[ 	]+cb 48[       	]+bit 1,b
>+[  ]+72:[ 	]+cb 49[       	]+bit 1,c
>+[  ]+74:[ 	]+cb 4a[       	]+bit 1,d
>+[  ]+76:[ 	]+cb 4b[       	]+bit 1,e
>+[  ]+78:[ 	]+cb 4c[       	]+bit 1,h
>+[  ]+7a:[ 	]+cb 4d[       	]+bit 1,l
>+[  ]+7c:[ 	]+cb 56[       	]+bit 2,$hl$
>+[  ]+7e:[ 	]+dd cb 09 56[ 	]+bit 2,$ix\+9$
>+[  ]+82:[ 	]+fd cb 09 56[ 	]+bit 2,$iy\+9$
>+[  ]+86:[ 	]+cb 57[       	]+bit 2,a
>+[  ]+88:[ 	]+cb 50[       	]+bit 2,b
>+[  ]+8a:[ 	]+cb 51[       	]+bit 2,c
>+[  ]+8c:[ 	]+cb 52[       	]+bit 2,d
>+[  ]+8e:[ 	]+cb 53[       	]+bit 2,e
>+[  ]+90:[ 	]+cb 54[       	]+bit 2,h
>+[  ]+92:[ 	]+cb 55[       	]+bit 2,l
>+[  ]+94:[ 	]+cb 5e[       	]+bit 3,$hl$
>+[  ]+96:[ 	]+dd cb 09 5e[ 	]+bit 3,$ix\+9$
>+[  ]+9a:[ 	]+fd cb 09 5e[ 	]+bit 3,$iy\+9$
>+[  ]+9e:[ 	]+cb 5f[       	]+bit 3,a
>+[  ]+a0:[ 	]+cb 58[       	]+bit 3,b
>+[  ]+a2:[ 	]+cb 59[       	]+bit 3,c
>+[  ]+a4:[ 	]+cb 5a[       	]+bit 3,d
>+[  ]+a6:[ 	]+cb 5b[       	]+bit 3,e
>+[  ]+a8:[ 	]+cb 5c[       	]+bit 3,h
>+[  ]+aa:[ 	]+cb 5d[       	]+bit 3,l
>+[  ]+ac:[ 	]+cb 66[       	]+bit 4,$hl$
>+[  ]+ae:[ 	]+dd cb 09 66[ 	]+bit 4,$ix\+9$
>+[  ]+b2:[ 	]+fd cb 09 66[ 	]+bit 4,$iy\+9$
>+[  ]+b6:[ 	]+cb 67[       	]+bit 4,a
>+[  ]+b8:[ 	]+cb 60[       	]+bit 4,b
>+[  ]+ba:[ 	]+cb 61[       	]+bit 4,c
>+[  ]+bc:[ 	]+cb 62[       	]+bit 4,d
>+[  ]+be:[ 	]+cb 63[       	]+bit 4,e
>+[  ]+c0:[ 	]+cb 64[       	]+bit 4,h
>+[  ]+c2:[ 	]+cb 65[       	]+bit 4,l
>+[  ]+c4:[ 	]+cb 6e[       	]+bit 5,$hl$
>+[  ]+c6:[ 	]+dd cb 09 6e[ 	]+bit 5,$ix\+9$
>+[  ]+ca:[ 	]+fd cb 09 6e[ 	]+bit 5,$iy\+9$
>+[  ]+ce:[ 	]+cb 6f[       	]+bit 5,a
>+[  ]+d0:[ 	]+cb 68[       	]+bit 5,b
>+[  ]+d2:[ 	]+cb 69[       	]+bit 5,c
>+[  ]+d4:[ 	]+cb 6a[       	]+bit 5,d
>+[  ]+d6:[ 	]+cb 6b[       	]+bit 5,e
>+[  ]+d8:[ 	]+cb 6c[       	]+bit 5,h
>+[  ]+da:[ 	]+cb 6d[       	]+bit 5,l
>+[  ]+dc:[ 	]+cb 76[       	]+bit 6,$hl$
>+[  ]+de:[ 	]+dd cb 09 76[ 	]+bit 6,$ix\+9$
>+[  ]+e2:[ 	]+fd cb 09 76[ 	]+bit 6,$iy\+9$
>+[  ]+e6:[ 	]+cb 77[       	]+bit 6,a
>+[  ]+e8:[ 	]+cb 70[       	]+bit 6,b
>+[  ]+ea:[ 	]+cb 71[       	]+bit 6,c
>+[  ]+ec:[ 	]+cb 72[       	]+bit 6,d
>+[  ]+ee:[ 	]+cb 73[       	]+bit 6,e
>+[  ]+f0:[ 	]+cb 74[       	]+bit 6,h
>+[  ]+f2:[ 	]+cb 75[       	]+bit 6,l
>+[  ]+f4:[ 	]+cb 7e[       	]+bit 7,$hl$
>+[  ]+f6:[ 	]+dd cb 09 7e[ 	]+bit 7,$ix\+9$
>+[  ]+fa:[ 	]+fd cb 09 7e[ 	]+bit 7,$iy\+9$
>+[  ]+fe:[ 	]+cb 7f[       	]+bit 7,a
>+[ ]+100:[ 	]+cb 78[       	]+bit 7,b
>+[ ]+102:[ 	]+cb 79[       	]+bit 7,c
>+[ ]+104:[ 	]+cb 7a[       	]+bit 7,d
>+[ ]+106:[ 	]+cb 7b[       	]+bit 7,e
>+[ ]+108:[ 	]+cb 7c[       	]+bit 7,h
>+[ ]+10a:[ 	]+cb 7d[       	]+bit 7,l
>+[ ]+10c:[ 	]+cd 34 12[    	]+call 0x1234
>+[ ]+10f:[ 	]+dc 34 12[    	]+call c,0x1234
>+[ ]+112:[ 	]+fc 34 12[    	]+call m,0x1234
>+[ ]+115:[ 	]+d4 34 12[    	]+call nc,0x1234
>+[ ]+118:[ 	]+c4 34 12[    	]+call nz,0x1234
>+[ ]+11b:[ 	]+f4 34 12[    	]+call p,0x1234
>+[ ]+11e:[ 	]+ec 34 12[    	]+call pe,0x1234
>+[ ]+121:[ 	]+e4 34 12[    	]+call po,0x1234
>+[ ]+124:[ 	]+cc 34 12[    	]+call z,0x1234
>+[ ]+127:[ 	]+3f[          	]+ccf
>+[ ]+128:[ 	]+be[          	]+cp $hl$
>+[ ]+129:[ 	]+dd be 09[    	]+cp $ix\+9$
>+[ ]+12c:[ 	]+fd be 09[    	]+cp $iy\+9$
>+[ ]+12f:[ 	]+fe 03[       	]+cp 0x03
>+[ ]+131:[ 	]+bf[          	]+cp a
>+[ ]+132:[ 	]+b8[          	]+cp b
>+[ ]+133:[ 	]+b9[          	]+cp c
>+[ ]+134:[ 	]+ba[          	]+cp d
>+[ ]+135:[ 	]+bb[          	]+cp e
>+[ ]+136:[ 	]+bc[          	]+cp h
>+[ ]+137:[ 	]+bd[          	]+cp l
>+[ ]+138:[ 	]+ed a9[       	]+cpd
>+[ ]+13a:[ 	]+ed b9[       	]+cpdr
>+[ ]+13c:[ 	]+ed a1[       	]+cpi
>+[ ]+13e:[ 	]+ed b1[       	]+cpir
>+[ ]+140:[ 	]+2f[          	]+cpl
>+[ ]+141:[ 	]+27[          	]+daa
>+[ ]+142:[ 	]+35[          	]+dec $hl$
>+[ ]+143:[ 	]+dd 35 09[    	]+dec $ix\+9$
>+[ ]+146:[ 	]+fd 35 09[    	]+dec $iy\+9$
>+[ ]+149:[ 	]+3d[          	]+dec a
>+[ ]+14a:[ 	]+05[          	]+dec b
>+[ ]+14b:[ 	]+0b[          	]+dec bc
>+[ ]+14c:[ 	]+0d[          	]+dec c
>+[ ]+14d:[ 	]+15[          	]+dec d
>+[ ]+14e:[ 	]+1b[          	]+dec de
>+[ ]+14f:[ 	]+1d[          	]+dec e
>+[ ]+150:[ 	]+25[          	]+dec h
>+[ ]+151:[ 	]+2b[          	]+dec hl
>+[ ]+152:[ 	]+dd 2b[       	]+dec ix
>+[ ]+154:[ 	]+fd 2b[       	]+dec iy
>+[ ]+156:[ 	]+2d[          	]+dec l
>+[ ]+157:[ 	]+3b[          	]+dec sp
>+[ ]+158:[ 	]+f3[          	]+di
>+[ ]+159:[ 	]+10 05[       	]+djnz 0x0160
>+[ ]+15b:[ 	]+fb[          	]+ei
>+[ ]+15c:[ 	]+e3[          	]+ex $sp$,hl
>+[ ]+15d:[ 	]+dd e3[       	]+ex $sp$,ix
>+[ ]+15f:[ 	]+fd e3[       	]+ex $sp$,iy
>+[ ]+161:[ 	]+08[          	]+ex af,af'
>+[ ]+162:[ 	]+eb[          	]+ex de,hl
>+[ ]+163:[ 	]+d9[          	]+exx
>+[ ]+164:[ 	]+76[          	]+halt
>+[ ]+165:[ 	]+ed 46[       	]+im 0
>+[ ]+167:[ 	]+ed 56[       	]+im 1
>+[ ]+169:[ 	]+ed 5e[       	]+im 2
>+[ ]+16b:[ 	]+ed 78[       	]+in a,$c$
>+[ ]+16d:[ 	]+db 03[       	]+in a,$0x03$
>+[ ]+16f:[ 	]+ed 40[       	]+in b,$c$
>+[ ]+171:[ 	]+ed 48[       	]+in c,$c$
>+[ ]+173:[ 	]+ed 50[       	]+in d,$c$
>+[ ]+175:[ 	]+ed 58[       	]+in e,$c$
>+[ ]+177:[ 	]+ed 60[       	]+in h,$c$
>+[ ]+179:[ 	]+ed 68[       	]+in l,$c$
>+[ ]+17b:[ 	]+34[          	]+inc $hl$
>+[ ]+17c:[ 	]+dd 34 09[    	]+inc $ix\+9$
>+[ ]+17f:[ 	]+fd 34 09[    	]+inc $iy\+9$
>+[ ]+182:[ 	]+3c[          	]+inc a
>+[ ]+183:[ 	]+04[          	]+inc b
>+[ ]+184:[ 	]+03[          	]+inc bc
>+[ ]+185:[ 	]+0c[          	]+inc c
>+[ ]+186:[ 	]+14[          	]+inc d
>+[ ]+187:[ 	]+13[          	]+inc de
>+[ ]+188:[ 	]+1c[          	]+inc e
>+[ ]+189:[ 	]+24[          	]+inc h
>+[ ]+18a:[ 	]+23[          	]+inc hl
>+[ ]+18b:[ 	]+dd 23[       	]+inc ix
>+[ ]+18d:[ 	]+fd 23[       	]+inc iy
>+[ ]+18f:[ 	]+2c[          	]+inc l
>+[ ]+190:[ 	]+33[          	]+inc sp
>+[ ]+191:[ 	]+ed aa[       	]+ind
>+[ ]+193:[ 	]+ed ba[       	]+indr
>+[ ]+195:[ 	]+ed a2[       	]+ini
>+[ ]+197:[ 	]+ed b2[       	]+inir
>+[ ]+199:[ 	]+e9[          	]+jp $hl$
>+[ ]+19a:[ 	]+dd e9[       	]+jp $ix$
>+[ ]+19c:[ 	]+fd e9[       	]+jp $iy$
>+[ ]+19e:[ 	]+c3 34 12[    	]+jp 0x1234
>+[ ]+1a1:[ 	]+da 34 12[    	]+jp c,0x1234
>+[ ]+1a4:[ 	]+fa 34 12[    	]+jp m,0x1234
>+[ ]+1a7:[ 	]+d2 34 12[    	]+jp nc,0x1234
>+[ ]+1aa:[ 	]+c2 34 12[    	]+jp nz,0x1234
>+[ ]+1ad:[ 	]+f2 34 12[    	]+jp p,0x1234
>+[ ]+1b0:[ 	]+ea 34 12[    	]+jp pe,0x1234
>+[ ]+1b3:[ 	]+e2 34 12[    	]+jp po,0x1234
>+[ ]+1b6:[ 	]+ca 34 12[    	]+jp z,0x1234
>+[ ]+1b9:[ 	]+18 05[       	]+jr 0x01c0
>+[ ]+1bb:[ 	]+38 05[       	]+jr c,0x01c2
>+[ ]+1bd:[ 	]+30 05[       	]+jr nc,0x01c4
>+[ ]+1bf:[ 	]+20 05[       	]+jr nz,0x01c6
>+[ ]+1c1:[ 	]+28 05[       	]+jr z,0x01c8
>+[ ]+1c3:[ 	]+32 34 12[    	]+ld $0x1234$,a
>+[ ]+1c6:[ 	]+ed 43 34 12[ 	]+ld $0x1234$,bc
>+[ ]+1ca:[ 	]+ed 53 34 12[ 	]+ld $0x1234$,de
>+[ ]+1ce:[ 	]+22 34 12[    	]+ld $0x1234$,hl
>+[ ]+1d1:[ 	]+dd 22 34 12[ 	]+ld $0x1234$,ix
>+[ ]+1d5:[ 	]+fd 22 34 12[ 	]+ld $0x1234$,iy
>+[ ]+1d9:[ 	]+ed 73 34 12[ 	]+ld $0x1234$,sp
>+[ ]+1dd:[ 	]+02[          	]+ld $bc$,a
>+[ ]+1de:[ 	]+12[          	]+ld $de$,a
>+[ ]+1df:[ 	]+36 03[       	]+ld $hl$,0x03
>+[ ]+1e1:[ 	]+77[          	]+ld $hl$,a
>+[ ]+1e2:[ 	]+70[          	]+ld $hl$,b
>+[ ]+1e3:[ 	]+71[          	]+ld $hl$,c
>+[ ]+1e4:[ 	]+72[          	]+ld $hl$,d
>+[ ]+1e5:[ 	]+73[          	]+ld $hl$,e
>+[ ]+1e6:[ 	]+74[          	]+ld $hl$,h
>+[ ]+1e7:[ 	]+75[          	]+ld $hl$,l
>+[ ]+1e8:[ 	]+dd 36 09 03[ 	]+ld $ix\+9$,0x03
>+[ ]+1ec:[ 	]+dd 77 09[    	]+ld $ix\+9$,a
>+[ ]+1ef:[ 	]+dd 70 09[    	]+ld $ix\+9$,b
>+[ ]+1f2:[ 	]+dd 71 09[    	]+ld $ix\+9$,c
>+[ ]+1f5:[ 	]+dd 72 09[    	]+ld $ix\+9$,d
>+[ ]+1f8:[ 	]+dd 73 09[    	]+ld $ix\+9$,e
>+[ ]+1fb:[ 	]+dd 74 09[    	]+ld $ix\+9$,h
>+[ ]+1fe:[ 	]+dd 75 09[    	]+ld $ix\+9$,l
>+[ ]+201:[ 	]+fd 36 09 03[ 	]+ld $iy\+9$,0x03
>+[ ]+205:[ 	]+fd 77 09[    	]+ld $iy\+9$,a
>+[ ]+208:[ 	]+fd 70 09[    	]+ld $iy\+9$,b
>+[ ]+20b:[ 	]+fd 71 09[    	]+ld $iy\+9$,c
>+[ ]+20e:[ 	]+fd 72 09[    	]+ld $iy\+9$,d
>+[ ]+211:[ 	]+fd 73 09[    	]+ld $iy\+9$,e
>+[ ]+214:[ 	]+fd 74 09[    	]+ld $iy\+9$,h
>+[ ]+217:[ 	]+fd 75 09[    	]+ld $iy\+9$,l
>+[ ]+21a:[ 	]+3a 34 12[    	]+ld a,$0x1234$
>+[ ]+21d:[ 	]+0a[          	]+ld a,$bc$
>+[ ]+21e:[ 	]+1a[          	]+ld a,$de$
>+[ ]+21f:[ 	]+7e[          	]+ld a,$hl$
>+[ ]+220:[ 	]+dd 7e 09[    	]+ld a,$ix\+9$
>+[ ]+223:[ 	]+fd 7e 09[    	]+ld a,$iy\+9$
>+[ ]+226:[ 	]+3e 03[       	]+ld a,0x03
>+[ ]+228:[ 	]+7f[          	]+ld a,a
>+[ ]+229:[ 	]+78[          	]+ld a,b
>+[ ]+22a:[ 	]+79[          	]+ld a,c
>+[ ]+22b:[ 	]+7a[          	]+ld a,d
>+[ ]+22c:[ 	]+7b[          	]+ld a,e
>+[ ]+22d:[ 	]+7c[          	]+ld a,h
>+[ ]+22e:[ 	]+ed 57[       	]+ld a,i
>+[ ]+230:[ 	]+7d[          	]+ld a,l
>+[ ]+231:[ 	]+ed 5f[       	]+ld a,r
>+[ ]+233:[ 	]+46[          	]+ld b,$hl$
>+[ ]+234:[ 	]+dd 46 09[    	]+ld b,$ix\+9$
>+[ ]+237:[ 	]+fd 46 09[    	]+ld b,$iy\+9$
>+[ ]+23a:[ 	]+06 03[       	]+ld b,0x03
>+[ ]+23c:[ 	]+47[          	]+ld b,a
>+[ ]+23d:[ 	]+40[          	]+ld b,b
>+[ ]+23e:[ 	]+41[          	]+ld b,c
>+[ ]+23f:[ 	]+42[          	]+ld b,d
>+[ ]+240:[ 	]+43[          	]+ld b,e
>+[ ]+241:[ 	]+44[          	]+ld b,h
>+[ ]+242:[ 	]+45[          	]+ld b,l
>+[ ]+243:[ 	]+ed 4b 34 12[ 	]+ld bc,$0x1234$
>+[ ]+247:[ 	]+01 34 12[    	]+ld bc,0x1234
>+[ ]+24a:[ 	]+4e[          	]+ld c,$hl$
>+[ ]+24b:[ 	]+dd 4e 09[    	]+ld c,$ix\+9$
>+[ ]+24e:[ 	]+fd 4e 09[    	]+ld c,$iy\+9$
>+[ ]+251:[ 	]+0e 03[       	]+ld c,0x03
>+[ ]+253:[ 	]+4f[          	]+ld c,a
>+[ ]+254:[ 	]+48[          	]+ld c,b
>+[ ]+255:[ 	]+49[          	]+ld c,c
>+[ ]+256:[ 	]+4a[          	]+ld c,d
>+[ ]+257:[ 	]+4b[          	]+ld c,e
>+[ ]+258:[ 	]+4c[          	]+ld c,h
>+[ ]+259:[ 	]+4d[          	]+ld c,l
>+[ ]+25a:[ 	]+56[          	]+ld d,$hl$
>+[ ]+25b:[ 	]+dd 56 09[    	]+ld d,$ix\+9$
>+[ ]+25e:[ 	]+fd 56 09[    	]+ld d,$iy\+9$
>+[ ]+261:[ 	]+16 03[       	]+ld d,0x03
>+[ ]+263:[ 	]+57[          	]+ld d,a
>+[ ]+264:[ 	]+50[          	]+ld d,b
>+[ ]+265:[ 	]+51[          	]+ld d,c
>+[ ]+266:[ 	]+52[          	]+ld d,d
>+[ ]+267:[ 	]+53[          	]+ld d,e
>+[ ]+268:[ 	]+54[          	]+ld d,h
>+[ ]+269:[ 	]+55[          	]+ld d,l
>+[ ]+26a:[ 	]+ed 5b 34 12[ 	]+ld de,$0x1234$
>+[ ]+26e:[ 	]+11 34 12[    	]+ld de,0x1234
>+[ ]+271:[ 	]+5e[          	]+ld e,$hl$
>+[ ]+272:[ 	]+dd 5e 09[    	]+ld e,$ix\+9$
>+[ ]+275:[ 	]+fd 5e 09[    	]+ld e,$iy\+9$
>+[ ]+278:[ 	]+1e 03[       	]+ld e,0x03
>+[ ]+27a:[ 	]+5f[          	]+ld e,a
>+[ ]+27b:[ 	]+58[          	]+ld e,b
>+[ ]+27c:[ 	]+59[          	]+ld e,c
>+[ ]+27d:[ 	]+5a[          	]+ld e,d
>+[ ]+27e:[ 	]+5b[          	]+ld e,e
>+[ ]+27f:[ 	]+5c[          	]+ld e,h
>+[ ]+280:[ 	]+5d[          	]+ld e,l
>+[ ]+281:[ 	]+66[          	]+ld h,$hl$
>+[ ]+282:[ 	]+dd 66 09[    	]+ld h,$ix\+9$
>+[ ]+285:[ 	]+fd 66 09[    	]+ld h,$iy\+9$
>+[ ]+288:[ 	]+26 03[       	]+ld h,0x03
>+[ ]+28a:[ 	]+67[          	]+ld h,a
>+[ ]+28b:[ 	]+60[          	]+ld h,b
>+[ ]+28c:[ 	]+61[          	]+ld h,c
>+[ ]+28d:[ 	]+62[          	]+ld h,d
>+[ ]+28e:[ 	]+63[          	]+ld h,e
>+[ ]+28f:[ 	]+64[          	]+ld h,h
>+[ ]+290:[ 	]+65[          	]+ld h,l
>+[ ]+291:[ 	]+2a 34 12[    	]+ld hl,$0x1234$
>+[ ]+294:[ 	]+21 34 12[    	]+ld hl,0x1234
>+[ ]+297:[ 	]+ed 47[       	]+ld i,a
>+[ ]+299:[ 	]+dd 2a 34 12[ 	]+ld ix,$0x1234$
>+[ ]+29d:[ 	]+dd 21 34 12[ 	]+ld ix,0x1234
>+[ ]+2a1:[ 	]+fd 2a 34 12[ 	]+ld iy,$0x1234$
>+[ ]+2a5:[ 	]+fd 21 34 12[ 	]+ld iy,0x1234
>+[ ]+2a9:[ 	]+6e[          	]+ld l,$hl$
>+[ ]+2aa:[ 	]+dd 6e 09[    	]+ld l,$ix\+9$
>+[ ]+2ad:[ 	]+fd 6e 09[    	]+ld l,$iy\+9$
>+[ ]+2b0:[ 	]+2e 03[       	]+ld l,0x03
>+[ ]+2b2:[ 	]+6f[          	]+ld l,a
>+[ ]+2b3:[ 	]+68[          	]+ld l,b
>+[ ]+2b4:[ 	]+69[          	]+ld l,c
>+[ ]+2b5:[ 	]+6a[          	]+ld l,d
>+[ ]+2b6:[ 	]+6b[          	]+ld l,e
>+[ ]+2b7:[ 	]+6c[          	]+ld l,h
>+[ ]+2b8:[ 	]+6d[          	]+ld l,l
>+[ ]+2b9:[ 	]+ed 4f[       	]+ld r,a
>+[ ]+2bb:[ 	]+ed 7b 34 12[ 	]+ld sp,$0x1234$
>+[ ]+2bf:[ 	]+31 34 12[    	]+ld sp,0x1234
>+[ ]+2c2:[ 	]+f9[          	]+ld sp,hl
>+[ ]+2c3:[ 	]+dd f9[       	]+ld sp,ix
>+[ ]+2c5:[ 	]+fd f9[       	]+ld sp,iy
>+[ ]+2c7:[ 	]+ed a8[       	]+ldd
>+[ ]+2c9:[ 	]+ed b8[       	]+lddr
>+[ ]+2cb:[ 	]+ed a0[       	]+ldi
>+[ ]+2cd:[ 	]+ed b0[       	]+ldir
>+[ ]+2cf:[ 	]+ed 44[       	]+neg
>+[ ]+2d1:[ 	]+00[          	]+nop
>+[ ]+2d2:[ 	]+b6[          	]+or $hl$
>+[ ]+2d3:[ 	]+dd b6 09[    	]+or $ix\+9$
>+[ ]+2d6:[ 	]+fd b6 09[    	]+or $iy\+9$
>+[ ]+2d9:[ 	]+f6 03[       	]+or 0x03
>+[ ]+2db:[ 	]+b7[          	]+or a
>+[ ]+2dc:[ 	]+b0[          	]+or b
>+[ ]+2dd:[ 	]+b1[          	]+or c
>+[ ]+2de:[ 	]+b2[          	]+or d
>+[ ]+2df:[ 	]+b3[          	]+or e
>+[ ]+2e0:[ 	]+b4[          	]+or h
>+[ ]+2e1:[ 	]+b5[          	]+or l
>+[ ]+2e2:[ 	]+ed bb[       	]+otdr
>+[ ]+2e4:[ 	]+ed b3[       	]+otir
>+[ ]+2e6:[ 	]+ed 79[       	]+out $c$,a
>+[ ]+2e8:[ 	]+ed 41[       	]+out $c$,b
>+[ ]+2ea:[ 	]+ed 49[       	]+out $c$,c
>+[ ]+2ec:[ 	]+ed 51[       	]+out $c$,d
>+[ ]+2ee:[ 	]+ed 59[       	]+out $c$,e
>+[ ]+2f0:[ 	]+ed 61[       	]+out $c$,h
>+[ ]+2f2:[ 	]+ed 69[       	]+out $c$,l
>+[ ]+2f4:[ 	]+d3 03[       	]+out $0x03$,a
>+[ ]+2f6:[ 	]+ed ab[       	]+outd
>+[ ]+2f8:[ 	]+ed a3[       	]+outi
>+[ ]+2fa:[ 	]+f1[          	]+pop af
>+[ ]+2fb:[ 	]+c1[          	]+pop bc
>+[ ]+2fc:[ 	]+d1[          	]+pop de
>+[ ]+2fd:[ 	]+e1[          	]+pop hl
>+[ ]+2fe:[ 	]+dd e1[       	]+pop ix
>+[ ]+300:[ 	]+fd e1[       	]+pop iy
>+[ ]+302:[ 	]+f5[          	]+push af
>+[ ]+303:[ 	]+c5[          	]+push bc
>+[ ]+304:[ 	]+d5[          	]+push de
>+[ ]+305:[ 	]+e5[          	]+push hl
>+[ ]+306:[ 	]+dd e5[       	]+push ix
>+[ ]+308:[ 	]+fd e5[       	]+push iy
>+[ ]+30a:[ 	]+cb 86[       	]+res 0,$hl$
>+[ ]+30c:[ 	]+dd cb 09 86[ 	]+res 0,$ix\+9$
>+[ ]+310:[ 	]+fd cb 09 86[ 	]+res 0,$iy\+9$
>+[ ]+314:[ 	]+cb 87[       	]+res 0,a
>+[ ]+316:[ 	]+cb 80[       	]+res 0,b
>+[ ]+318:[ 	]+cb 81[       	]+res 0,c
>+[ ]+31a:[ 	]+cb 82[       	]+res 0,d
>+[ ]+31c:[ 	]+cb 83[       	]+res 0,e
>+[ ]+31e:[ 	]+cb 84[       	]+res 0,h
>+[ ]+320:[ 	]+cb 85[       	]+res 0,l
>+[ ]+322:[ 	]+cb 8e[       	]+res 1,$hl$
>+[ ]+324:[ 	]+dd cb 09 8e[ 	]+res 1,$ix\+9$
>+[ ]+328:[ 	]+fd cb 09 8e[ 	]+res 1,$iy\+9$
>+[ ]+32c:[ 	]+cb 8f[       	]+res 1,a
>+[ ]+32e:[ 	]+cb 88[       	]+res 1,b
>+[ ]+330:[ 	]+cb 89[       	]+res 1,c
>+[ ]+332:[ 	]+cb 8a[       	]+res 1,d
>+[ ]+334:[ 	]+cb 8b[       	]+res 1,e
>+[ ]+336:[ 	]+cb 8c[       	]+res 1,h
>+[ ]+338:[ 	]+cb 8d[       	]+res 1,l
>+[ ]+33a:[ 	]+cb 96[       	]+res 2,$hl$
>+[ ]+33c:[ 	]+dd cb 09 96[ 	]+res 2,$ix\+9$
>+[ ]+340:[ 	]+fd cb 09 96[ 	]+res 2,$iy\+9$
>+[ ]+344:[ 	]+cb 97[       	]+res 2,a
>+[ ]+346:[ 	]+cb 90[       	]+res 2,b
>+[ ]+348:[ 	]+cb 91[       	]+res 2,c
>+[ ]+34a:[ 	]+cb 92[       	]+res 2,d
>+[ ]+34c:[ 	]+cb 93[       	]+res 2,e
>+[ ]+34e:[ 	]+cb 94[       	]+res 2,h
>+[ ]+350:[ 	]+cb 95[       	]+res 2,l
>+[ ]+352:[ 	]+cb 9e[       	]+res 3,$hl$
>+[ ]+354:[ 	]+dd cb 09 9e[ 	]+res 3,$ix\+9$
>+[ ]+358:[ 	]+fd cb 09 9e[ 	]+res 3,$iy\+9$
>+[ ]+35c:[ 	]+cb 9f[       	]+res 3,a
>+[ ]+35e:[ 	]+cb 98[       	]+res 3,b
>+[ ]+360:[ 	]+cb 99[       	]+res 3,c
>+[ ]+362:[ 	]+cb 9a[       	]+res 3,d
>+[ ]+364:[ 	]+cb 9b[       	]+res 3,e
>+[ ]+366:[ 	]+cb 9c[       	]+res 3,h
>+[ ]+368:[ 	]+cb 9d[       	]+res 3,l
>+[ ]+36a:[ 	]+cb a6[       	]+res 4,$hl$
>+[ ]+36c:[ 	]+dd cb 09 a6[ 	]+res 4,$ix\+9$
>+[ ]+370:[ 	]+fd cb 09 a6[ 	]+res 4,$iy\+9$
>+[ ]+374:[ 	]+cb a7[       	]+res 4,a
>+[ ]+376:[ 	]+cb a0[       	]+res 4,b
>+[ ]+378:[ 	]+cb a1[       	]+res 4,c
>+[ ]+37a:[ 	]+cb a2[       	]+res 4,d
>+[ ]+37c:[ 	]+cb a3[       	]+res 4,e
>+[ ]+37e:[ 	]+cb a4[       	]+res 4,h
>+[ ]+380:[ 	]+cb a5[       	]+res 4,l
>+[ ]+382:[ 	]+cb ae[       	]+res 5,$hl$
>+[ ]+384:[ 	]+dd cb 09 ae[ 	]+res 5,$ix\+9$
>+[ ]+388:[ 	]+fd cb 09 ae[ 	]+res 5,$iy\+9$
>+[ ]+38c:[ 	]+cb af[       	]+res 5,a
>+[ ]+38e:[ 	]+cb a8[       	]+res 5,b
>+[ ]+390:[ 	]+cb a9[       	]+res 5,c
>+[ ]+392:[ 	]+cb aa[       	]+res 5,d
>+[ ]+394:[ 	]+cb ab[       	]+res 5,e
>+[ ]+396:[ 	]+cb ac[       	]+res 5,h
>+[ ]+398:[ 	]+cb ad[       	]+res 5,l
>+[ ]+39a:[ 	]+cb b6[       	]+res 6,$hl$
>+[ ]+39c:[ 	]+dd cb 09 b6[ 	]+res 6,$ix\+9$
>+[ ]+3a0:[ 	]+fd cb 09 b6[ 	]+res 6,$iy\+9$
>+[ ]+3a4:[ 	]+cb b7[       	]+res 6,a
>+[ ]+3a6:[ 	]+cb b0[       	]+res 6,b
>+[ ]+3a8:[ 	]+cb b1[       	]+res 6,c
>+[ ]+3aa:[ 	]+cb b2[       	]+res 6,d
>+[ ]+3ac:[ 	]+cb b3[       	]+res 6,e
>+[ ]+3ae:[ 	]+cb b4[       	]+res 6,h
>+[ ]+3b0:[ 	]+cb b5[       	]+res 6,l
>+[ ]+3b2:[ 	]+cb be[       	]+res 7,$hl$
>+[ ]+3b4:[ 	]+dd cb 09 be[ 	]+res 7,$ix\+9$
>+[ ]+3b8:[ 	]+fd cb 09 be[ 	]+res 7,$iy\+9$
>+[ ]+3bc:[ 	]+cb bf[       	]+res 7,a
>+[ ]+3be:[ 	]+cb b8[       	]+res 7,b
>+[ ]+3c0:[ 	]+cb b9[       	]+res 7,c
>+[ ]+3c2:[ 	]+cb ba[       	]+res 7,d
>+[ ]+3c4:[ 	]+cb bb[       	]+res 7,e
>+[ ]+3c6:[ 	]+cb bc[       	]+res 7,h
>+[ ]+3c8:[ 	]+cb bd[       	]+res 7,l
>+[ ]+3ca:[ 	]+c9[          	]+ret
>+[ ]+3cb:[ 	]+d8[          	]+ret c
>+[ ]+3cc:[ 	]+f8[          	]+ret m
>+[ ]+3cd:[ 	]+d0[          	]+ret nc
>+[ ]+3ce:[ 	]+c0[          	]+ret nz
>+[ ]+3cf:[ 	]+f0[          	]+ret p
>+[ ]+3d0:[ 	]+e8[          	]+ret pe
>+[ ]+3d1:[ 	]+e0[          	]+ret po
>+[ ]+3d2:[ 	]+c8[          	]+ret z
>+[ ]+3d3:[ 	]+ed 4d[       	]+reti
>+[ ]+3d5:[ 	]+ed 45[       	]+retn
>+[ ]+3d7:[ 	]+cb 16[       	]+rl $hl$
>+[ ]+3d9:[ 	]+dd cb 09 16[ 	]+rl $ix\+9$
>+[ ]+3dd:[ 	]+fd cb 09 16[ 	]+rl $iy\+9$
>+[ ]+3e1:[ 	]+cb 17[       	]+rl a
>+[ ]+3e3:[ 	]+cb 10[       	]+rl b
>+[ ]+3e5:[ 	]+cb 11[       	]+rl c
>+[ ]+3e7:[ 	]+cb 12[       	]+rl d
>+[ ]+3e9:[ 	]+cb 13[       	]+rl e
>+[ ]+3eb:[ 	]+cb 14[       	]+rl h
>+[ ]+3ed:[ 	]+cb 15[       	]+rl l
>+[ ]+3ef:[ 	]+17[          	]+rla
>+[ ]+3f0:[ 	]+cb 06[       	]+rlc $hl$
>+[ ]+3f2:[ 	]+dd cb 09 06[ 	]+rlc $ix\+9$
>+[ ]+3f6:[ 	]+fd cb 09 06[ 	]+rlc $iy\+9$
>+[ ]+3fa:[ 	]+cb 07[       	]+rlc a
>+[ ]+3fc:[ 	]+cb 00[       	]+rlc b
>+[ ]+3fe:[ 	]+cb 01[       	]+rlc c
>+[ ]+400:[ 	]+cb 02[       	]+rlc d
>+[ ]+402:[ 	]+cb 03[       	]+rlc e
>+[ ]+404:[ 	]+cb 04[       	]+rlc h
>+[ ]+406:[ 	]+cb 05[       	]+rlc l
>+[ ]+408:[ 	]+07[          	]+rlca
>+[ ]+409:[ 	]+ed 6f[       	]+rld
>+[ ]+40b:[ 	]+cb 1e[       	]+rr $hl$
>+[ ]+40d:[ 	]+dd cb 09 1e[ 	]+rr $ix\+9$
>+[ ]+411:[ 	]+fd cb 09 1e[ 	]+rr $iy\+9$
>+[ ]+415:[ 	]+cb 1f[       	]+rr a
>+[ ]+417:[ 	]+cb 18[       	]+rr b
>+[ ]+419:[ 	]+cb 19[       	]+rr c
>+[ ]+41b:[ 	]+cb 1a[       	]+rr d
>+[ ]+41d:[ 	]+cb 1b[       	]+rr e
>+[ ]+41f:[ 	]+cb 1c[       	]+rr h
>+[ ]+421:[ 	]+cb 1d[       	]+rr l
>+[ ]+423:[ 	]+1f[          	]+rra
>+[ ]+424:[ 	]+cb 0e[       	]+rrc $hl$
>+[ ]+426:[ 	]+dd cb 09 0e[ 	]+rrc $ix\+9$
>+[ ]+42a:[ 	]+fd cb 09 0e[ 	]+rrc $iy\+9$
>+[ ]+42e:[ 	]+cb 0f[       	]+rrc a
>+[ ]+430:[ 	]+cb 08[       	]+rrc b
>+[ ]+432:[ 	]+cb 09[       	]+rrc c
>+[ ]+434:[ 	]+cb 0a[       	]+rrc d
>+[ ]+436:[ 	]+cb 0b[       	]+rrc e
>+[ ]+438:[ 	]+cb 0c[       	]+rrc h
>+[ ]+43a:[ 	]+cb 0d[       	]+rrc l
>+[ ]+43c:[ 	]+0f[          	]+rrca
>+[ ]+43d:[ 	]+ed 67[       	]+rrd
>+[ ]+43f:[ 	]+c7[          	]+rst 0x00
>+[ ]+440:[ 	]+cf[          	]+rst 0x08
>+[ ]+441:[ 	]+d7[          	]+rst 0x10
>+[ ]+442:[ 	]+df[          	]+rst 0x18
>+[ ]+443:[ 	]+e7[          	]+rst 0x20
>+[ ]+444:[ 	]+ef[          	]+rst 0x28
>+[ ]+445:[ 	]+f7[          	]+rst 0x30
>+[ ]+446:[ 	]+ff[          	]+rst 0x38
>+[ ]+447:[ 	]+9e[          	]+sbc a,$hl$
>+[ ]+448:[ 	]+dd 9e 09[    	]+sbc a,$ix\+9$
>+[ ]+44b:[ 	]+fd 9e 09[    	]+sbc a,$iy\+9$
>+[ ]+44e:[ 	]+de 03[       	]+sbc a,0x03
>+[ ]+450:[ 	]+9f[          	]+sbc a,a
>+[ ]+451:[ 	]+98[          	]+sbc a,b
>+[ ]+452:[ 	]+99[          	]+sbc a,c
>+[ ]+453:[ 	]+9a[          	]+sbc a,d
>+[ ]+454:[ 	]+9b[          	]+sbc a,e
>+[ ]+455:[ 	]+9c[          	]+sbc a,h
>+[ ]+456:[ 	]+9d[          	]+sbc a,l
>+[ ]+457:[ 	]+ed 42[       	]+sbc hl,bc
>+[ ]+459:[ 	]+ed 52[       	]+sbc hl,de
>+[ ]+45b:[ 	]+ed 62[       	]+sbc hl,hl
>+[ ]+45d:[ 	]+ed 72[       	]+sbc hl,sp
>+[ ]+45f:[ 	]+37[          	]+scf
>+[ ]+460:[ 	]+cb c6[       	]+set 0,$hl$
>+[ ]+462:[ 	]+dd cb 09 c6[ 	]+set 0,$ix\+9$
>+[ ]+466:[ 	]+fd cb 09 c6[ 	]+set 0,$iy\+9$
>+[ ]+46a:[ 	]+cb c7[       	]+set 0,a
>+[ ]+46c:[ 	]+cb c0[       	]+set 0,b
>+[ ]+46e:[ 	]+cb c1[       	]+set 0,c
>+[ ]+470:[ 	]+cb c2[       	]+set 0,d
>+[ ]+472:[ 	]+cb c3[       	]+set 0,e
>+[ ]+474:[ 	]+cb c4[       	]+set 0,h
>+[ ]+476:[ 	]+cb c5[       	]+set 0,l
>+[ ]+478:[ 	]+cb ce[       	]+set 1,$hl$
>+[ ]+47a:[ 	]+dd cb 09 ce[ 	]+set 1,$ix\+9$
>+[ ]+47e:[ 	]+fd cb 09 ce[ 	]+set 1,$iy\+9$
>+[ ]+482:[ 	]+cb cf[       	]+set 1,a
>+[ ]+484:[ 	]+cb c8[       	]+set 1,b
>+[ ]+486:[ 	]+cb c9[       	]+set 1,c
>+[ ]+488:[ 	]+cb ca[       	]+set 1,d
>+[ ]+48a:[ 	]+cb cb[       	]+set 1,e
>+[ ]+48c:[ 	]+cb cc[       	]+set 1,h
>+[ ]+48e:[ 	]+cb cd[       	]+set 1,l
>+[ ]+490:[ 	]+cb d6[       	]+set 2,$hl$
>+[ ]+492:[ 	]+dd cb 09 d6[ 	]+set 2,$ix\+9$
>+[ ]+496:[ 	]+fd cb 09 d6[ 	]+set 2,$iy\+9$
>+[ ]+49a:[ 	]+cb d7[       	]+set 2,a
>+[ ]+49c:[ 	]+cb d0[       	]+set 2,b
>+[ ]+49e:[ 	]+cb d1[       	]+set 2,c
>+[ ]+4a0:[ 	]+cb d2[       	]+set 2,d
>+[ ]+4a2:[ 	]+cb d3[       	]+set 2,e
>+[ ]+4a4:[ 	]+cb d4[       	]+set 2,h
>+[ ]+4a6:[ 	]+cb d5[       	]+set 2,l
>+[ ]+4a8:[ 	]+cb de[       	]+set 3,$hl$
>+[ ]+4aa:[ 	]+dd cb 09 de[ 	]+set 3,$ix\+9$
>+[ ]+4ae:[ 	]+fd cb 09 de[ 	]+set 3,$iy\+9$
>+[ ]+4b2:[ 	]+cb df[       	]+set 3,a
>+[ ]+4b4:[ 	]+cb d8[       	]+set 3,b
>+[ ]+4b6:[ 	]+cb d9[       	]+set 3,c
>+[ ]+4b8:[ 	]+cb da[       	]+set 3,d
>+[ ]+4ba:[ 	]+cb db[       	]+set 3,e
>+[ ]+4bc:[ 	]+cb dc[       	]+set 3,h
>+[ ]+4be:[ 	]+cb dd[       	]+set 3,l
>+[ ]+4c0:[ 	]+cb e6[       	]+set 4,$hl$
>+[ ]+4c2:[ 	]+dd cb 09 e6[ 	]+set 4,$ix\+9$
>+[ ]+4c6:[ 	]+fd cb 09 e6[ 	]+set 4,$iy\+9$
>+[ ]+4ca:[ 	]+cb e7[       	]+set 4,a
>+[ ]+4cc:[ 	]+cb e0[       	]+set 4,b
>+[ ]+4ce:[ 	]+cb e1[       	]+set 4,c
>+[ ]+4d0:[ 	]+cb e2[       	]+set 4,d
>+[ ]+4d2:[ 	]+cb e3[       	]+set 4,e
>+[ ]+4d4:[ 	]+cb e4[       	]+set 4,h
>+[ ]+4d6:[ 	]+cb e5[       	]+set 4,l
>+[ ]+4d8:[ 	]+cb ee[       	]+set 5,$hl$
>+[ ]+4da:[ 	]+dd cb 09 ee[ 	]+set 5,$ix\+9$
>+[ ]+4de:[ 	]+fd cb 09 ee[ 	]+set 5,$iy\+9$
>+[ ]+4e2:[ 	]+cb ef[       	]+set 5,a
>+[ ]+4e4:[ 	]+cb e8[       	]+set 5,b
>+[ ]+4e6:[ 	]+cb e9[       	]+set 5,c
>+[ ]+4e8:[ 	]+cb ea[       	]+set 5,d
>+[ ]+4ea:[ 	]+cb eb[       	]+set 5,e
>+[ ]+4ec:[ 	]+cb ec[       	]+set 5,h
>+[ ]+4ee:[ 	]+cb ed[       	]+set 5,l
>+[ ]+4f0:[ 	]+cb f6[       	]+set 6,$hl$
>+[ ]+4f2:[ 	]+dd cb 09 f6[ 	]+set 6,$ix\+9$
>+[ ]+4f6:[ 	]+fd cb 09 f6[ 	]+set 6,$iy\+9$
>+[ ]+4fa:[ 	]+cb f7[       	]+set 6,a
>+[ ]+4fc:[ 	]+cb f0[       	]+set 6,b
>+[ ]+4fe:[ 	]+cb f1[       	]+set 6,c
>+[ ]+500:[ 	]+cb f2[       	]+set 6,d
>+[ ]+502:[ 	]+cb f3[       	]+set 6,e
>+[ ]+504:[ 	]+cb f4[       	]+set 6,h
>+[ ]+506:[ 	]+cb f5[       	]+set 6,l
>+[ ]+508:[ 	]+cb fe[       	]+set 7,$hl$
>+[ ]+50a:[ 	]+dd cb 09 fe[ 	]+set 7,$ix\+9$
>+[ ]+50e:[ 	]+fd cb 09 fe[ 	]+set 7,$iy\+9$
>+[ ]+512:[ 	]+cb ff[       	]+set 7,a
>+[ ]+514:[ 	]+cb f8[       	]+set 7,b
>+[ ]+516:[ 	]+cb f9[       	]+set 7,c
>+[ ]+518:[ 	]+cb fa[       	]+set 7,d
>+[ ]+51a:[ 	]+cb fb[       	]+set 7,e
>+[ ]+51c:[ 	]+cb fc[       	]+set 7,h
>+[ ]+51e:[ 	]+cb fd[       	]+set 7,l
>+[ ]+520:[ 	]+cb 26[       	]+sla $hl$
>+[ ]+522:[ 	]+dd cb 09 26[ 	]+sla $ix\+9$
>+[ ]+526:[ 	]+fd cb 09 26[ 	]+sla $iy\+9$
>+[ ]+52a:[ 	]+cb 27[       	]+sla a
>+[ ]+52c:[ 	]+cb 20[       	]+sla b
>+[ ]+52e:[ 	]+cb 21[       	]+sla c
>+[ ]+530:[ 	]+cb 22[       	]+sla d
>+[ ]+532:[ 	]+cb 23[       	]+sla e
>+[ ]+534:[ 	]+cb 24[       	]+sla h
>+[ ]+536:[ 	]+cb 25[       	]+sla l
>+[ ]+538:[ 	]+cb 2e[       	]+sra $hl$
>+[ ]+53a:[ 	]+dd cb 09 2e[ 	]+sra $ix\+9$
>+[ ]+53e:[ 	]+fd cb 09 2e[ 	]+sra $iy\+9$
>+[ ]+542:[ 	]+cb 2f[       	]+sra a
>+[ ]+544:[ 	]+cb 28[       	]+sra b
>+[ ]+546:[ 	]+cb 29[       	]+sra c
>+[ ]+548:[ 	]+cb 2a[       	]+sra d
>+[ ]+54a:[ 	]+cb 2b[       	]+sra e
>+[ ]+54c:[ 	]+cb 2c[       	]+sra h
>+[ ]+54e:[ 	]+cb 2d[       	]+sra l
>+[ ]+550:[ 	]+cb 3e[       	]+srl $hl$
>+[ ]+552:[ 	]+dd cb 09 3e[ 	]+srl $ix\+9$
>+[ ]+556:[ 	]+fd cb 09 3e[ 	]+srl $iy\+9$
>+[ ]+55a:[ 	]+cb 3f[       	]+srl a
>+[ ]+55c:[ 	]+cb 38[       	]+srl b
>+[ ]+55e:[ 	]+cb 39[       	]+srl c
>+[ ]+560:[ 	]+cb 3a[       	]+srl d
>+[ ]+562:[ 	]+cb 3b[       	]+srl e
>+[ ]+564:[ 	]+cb 3c[       	]+srl h
>+[ ]+566:[ 	]+cb 3d[       	]+srl l
>+[ ]+568:[ 	]+96[          	]+sub $hl$
>+[ ]+569:[ 	]+dd 96 09[    	]+sub $ix\+9$
>+[ ]+56c:[ 	]+fd 96 09[    	]+sub $iy\+9$
>+[ ]+56f:[ 	]+d6 03[       	]+sub 0x03
>+[ ]+571:[ 	]+97[          	]+sub a
>+[ ]+572:[ 	]+90[          	]+sub b
>+[ ]+573:[ 	]+91[          	]+sub c
>+[ ]+574:[ 	]+92[          	]+sub d
>+[ ]+575:[ 	]+93[          	]+sub e
>+[ ]+576:[ 	]+94[          	]+sub h
>+[ ]+577:[ 	]+95[          	]+sub l
>+[ ]+578:[ 	]+ae[          	]+xor $hl$
>+[ ]+579:[ 	]+dd ae 09[    	]+xor $ix\+9$
>+[ ]+57c:[ 	]+fd ae 09[    	]+xor $iy\+9$
>+[ ]+57f:[ 	]+ee 03[       	]+xor 0x03
>+[ ]+581:[ 	]+af[          	]+xor a
>+[ ]+582:[ 	]+a8[          	]+xor b
>+[ ]+583:[ 	]+a9[          	]+xor c
>+[ ]+584:[ 	]+aa[          	]+xor d
>+[ ]+585:[ 	]+ab[          	]+xor e
>+[ ]+586:[ 	]+ac[          	]+xor h
>+[ ]+587:[ 	]+ad[          	]+xor l
>+[ ]+588:[ 	]+dd 7c[       	]+ld a,ixh
>+[ ]+58a:[ 	]+dd 44[       	]+ld b,ixh
>+[ ]+58c:[ 	]+dd 4c[       	]+ld c,ixh
>+[ ]+58e:[ 	]+dd 54[       	]+ld d,ixh
>+[ ]+590:[ 	]+dd 5c[       	]+ld e,ixh
>+[ ]+592:[ 	]+dd 64[       	]+ld ixh,ixh
>+[ ]+594:[ 	]+dd 6c[       	]+ld ixl,ixh
>+[ ]+596:[ 	]+dd 7d[       	]+ld a,ixl
>+[ ]+598:[ 	]+dd 45[       	]+ld b,ixl
>+[ ]+59a:[ 	]+dd 4d[       	]+ld c,ixl
>+[ ]+59c:[ 	]+dd 55[       	]+ld d,ixl
>+[ ]+59e:[ 	]+dd 5d[       	]+ld e,ixl
>+[ ]+5a0:[ 	]+dd 65[       	]+ld ixh,ixl
>+[ ]+5a2:[ 	]+dd 6d[       	]+ld ixl,ixl
>+[ ]+5a4:[ 	]+fd 7c[       	]+ld a,iyh
>+[ ]+5a6:[ 	]+fd 44[       	]+ld b,iyh
>+[ ]+5a8:[ 	]+fd 4c[       	]+ld c,iyh
>+[ ]+5aa:[ 	]+fd 54[       	]+ld d,iyh
>+[ ]+5ac:[ 	]+fd 5c[       	]+ld e,iyh
>+[ ]+5ae:[ 	]+fd 64[       	]+ld iyh,iyh
>+[ ]+5b0:[ 	]+fd 6c[       	]+ld iyl,iyh
>+[ ]+5b2:[ 	]+fd 7d[       	]+ld a,iyl
>+[ ]+5b4:[ 	]+fd 45[       	]+ld b,iyl
>+[ ]+5b6:[ 	]+fd 4d[       	]+ld c,iyl
>+[ ]+5b8:[ 	]+fd 55[       	]+ld d,iyl
>+[ ]+5ba:[ 	]+fd 5d[       	]+ld e,iyl
>+[ ]+5bc:[ 	]+fd 65[       	]+ld iyh,iyl
>+[ ]+5be:[ 	]+fd 6d[       	]+ld iyl,iyl
>+[ ]+5c0:[ 	]+dd 67[       	]+ld ixh,a
>+[ ]+5c2:[ 	]+dd 60[       	]+ld ixh,b
>+[ ]+5c4:[ 	]+dd 61[       	]+ld ixh,c
>+[ ]+5c6:[ 	]+dd 62[       	]+ld ixh,d
>+[ ]+5c8:[ 	]+dd 63[       	]+ld ixh,e
>+[ ]+5ca:[ 	]+dd 64[       	]+ld ixh,ixh
>+[ ]+5cc:[ 	]+dd 65[       	]+ld ixh,ixl
>+[ ]+5ce:[ 	]+dd 26 19[    	]+ld ixh,0x19
>+[ ]+5d1:[ 	]+dd 6f[       	]+ld ixl,a
>+[ ]+5d3:[ 	]+dd 68[       	]+ld ixl,b
>+[ ]+5d5:[ 	]+dd 69[       	]+ld ixl,c
>+[ ]+5d7:[ 	]+dd 6a[       	]+ld ixl,d
>+[ ]+5d9:[ 	]+dd 6b[       	]+ld ixl,e
>+[ ]+5db:[ 	]+dd 6c[       	]+ld ixl,ixh
>+[ ]+5dd:[ 	]+dd 6d[       	]+ld ixl,ixl
>+[ ]+5df:[ 	]+dd 2e 19[    	]+ld ixl,0x19
>+[ ]+5e2:[ 	]+fd 67[       	]+ld iyh,a
>+[ ]+5e4:[ 	]+fd 60[       	]+ld iyh,b
>+[ ]+5e6:[ 	]+fd 61[       	]+ld iyh,c
>+[ ]+5e8:[ 	]+fd 62[       	]+ld iyh,d
>+[ ]+5ea:[ 	]+fd 63[       	]+ld iyh,e
>+[ ]+5ec:[ 	]+fd 64[       	]+ld iyh,iyh
>+[ ]+5ee:[ 	]+fd 65[       	]+ld iyh,iyl
>+[ ]+5f0:[ 	]+fd 26 19[    	]+ld iyh,0x19
>+[ ]+5f3:[ 	]+fd 6f[       	]+ld iyl,a
>+[ ]+5f5:[ 	]+fd 68[       	]+ld iyl,b
>+[ ]+5f7:[ 	]+fd 69[       	]+ld iyl,c
>+[ ]+5f9:[ 	]+fd 6a[       	]+ld iyl,d
>+[ ]+5fb:[ 	]+fd 6b[       	]+ld iyl,e
>+[ ]+5fd:[ 	]+fd 6c[       	]+ld iyl,iyh
>+[ ]+5ff:[ 	]+fd 6d[       	]+ld iyl,iyl
>+[ ]+601:[ 	]+fd 2e 19[    	]+ld iyl,0x19
>+[ ]+604:[ 	]+dd 84[       	]+add a,ixh
>+[ ]+606:[ 	]+dd 85[       	]+add a,ixl
>+[ ]+608:[ 	]+fd 84[       	]+add a,iyh
>+[ ]+60a:[ 	]+fd 85[       	]+add a,iyl
>+[ ]+60c:[ 	]+dd 8c[       	]+adc a,ixh
>+[ ]+60e:[ 	]+dd 8d[       	]+adc a,ixl
>+[ ]+610:[ 	]+fd 8c[       	]+adc a,iyh
>+[ ]+612:[ 	]+fd 8d[       	]+adc a,iyl
>+[ ]+614:[ 	]+dd bc[       	]+cp ixh
>+[ ]+616:[ 	]+dd bd[       	]+cp ixl
>+[ ]+618:[ 	]+fd bc[       	]+cp iyh
>+[ ]+61a:[ 	]+fd bd[       	]+cp iyl
>+[ ]+61c:[ 	]+dd 25[       	]+dec ixh
>+[ ]+61e:[ 	]+dd 2d[       	]+dec ixl
>+[ ]+620:[ 	]+fd 25[       	]+dec iyh
>+[ ]+622:[ 	]+fd 2d[       	]+dec iyl
>+[ ]+624:[ 	]+dd 24[       	]+inc ixh
>+[ ]+626:[ 	]+dd 2c[       	]+inc ixl
>+[ ]+628:[ 	]+fd 24[       	]+inc iyh
>+[ ]+62a:[ 	]+fd 2c[       	]+inc iyl
>+[ ]+62c:[ 	]+dd 9c[       	]+sbc a,ixh
>+[ ]+62e:[ 	]+dd 9d[       	]+sbc a,ixl
>+[ ]+630:[ 	]+fd 9c[       	]+sbc a,iyh
>+[ ]+632:[ 	]+fd 9d[       	]+sbc a,iyl
>+[ ]+634:[ 	]+dd 94[       	]+sub ixh
>+[ ]+636:[ 	]+dd 95[       	]+sub ixl
>+[ ]+638:[ 	]+fd 94[       	]+sub iyh
>+[ ]+63a:[ 	]+fd 95[       	]+sub iyl
>+[ ]+63c:[ 	]+dd a4[       	]+and ixh
>+[ ]+63e:[ 	]+dd a5[       	]+and ixl
>+[ ]+640:[ 	]+fd a4[       	]+and iyh
>+[ ]+642:[ 	]+fd a5[       	]+and iyl
>+[ ]+644:[ 	]+dd b4[       	]+or ixh
>+[ ]+646:[ 	]+dd b5[       	]+or ixl
>+[ ]+648:[ 	]+fd b4[       	]+or iyh
>+[ ]+64a:[ 	]+fd b5[       	]+or iyl
>+[ ]+64c:[ 	]+dd ac[       	]+xor ixh
>+[ ]+64e:[ 	]+dd ad[       	]+xor ixl
>+[ ]+650:[ 	]+fd ac[       	]+xor iyh
>+[ ]+652:[ 	]+fd ad[       	]+xor iyl
>+[ ]+654:[ 	]+ed 70[       	]+in f,$c$
>+[ ]+656:[ 	]+ed 70[       	]+in f,$c$
>+[ ]+658:[ 	]+ed 71[       	]+out $c$,0
>+[ ]+65a:[ 	]+dd cb 08 07[ 	]+rlc $ix\+8$,a
>+[ ]+65e:[ 	]+dd cb 08 00[ 	]+rlc $ix\+8$,b
>+[ ]+662:[ 	]+dd cb 08 01[ 	]+rlc $ix\+8$,c
>+[ ]+666:[ 	]+dd cb 08 02[ 	]+rlc $ix\+8$,d
>+[ ]+66a:[ 	]+dd cb 08 03[ 	]+rlc $ix\+8$,e
>+[ ]+66e:[ 	]+dd cb 08 04[ 	]+rlc $ix\+8$,h
>+[ ]+672:[ 	]+dd cb 08 05[ 	]+rlc $ix\+8$,l
>+[ ]+676:[ 	]+fd cb 08 07[ 	]+rlc $iy\+8$,a
>+[ ]+67a:[ 	]+fd cb 08 00[ 	]+rlc $iy\+8$,b
>+[ ]+67e:[ 	]+fd cb 08 01[ 	]+rlc $iy\+8$,c
>+[ ]+682:[ 	]+fd cb 08 02[ 	]+rlc $iy\+8$,d
>+[ ]+686:[ 	]+fd cb 08 03[ 	]+rlc $iy\+8$,e
>+[ ]+68a:[ 	]+fd cb 08 04[ 	]+rlc $iy\+8$,h
>+[ ]+68e:[ 	]+fd cb 08 05[ 	]+rlc $iy\+8$,l
>+[ ]+692:[ 	]+dd cb 08 0f[ 	]+rrc $ix\+8$,a
>+[ ]+696:[ 	]+dd cb 08 08[ 	]+rrc $ix\+8$,b
>+[ ]+69a:[ 	]+dd cb 08 09[ 	]+rrc $ix\+8$,c
>+[ ]+69e:[ 	]+dd cb 08 0a[ 	]+rrc $ix\+8$,d
>+[ ]+6a2:[ 	]+dd cb 08 0b[ 	]+rrc $ix\+8$,e
>+[ ]+6a6:[ 	]+dd cb 08 0c[ 	]+rrc $ix\+8$,h
>+[ ]+6aa:[ 	]+dd cb 08 0d[ 	]+rrc $ix\+8$,l
>+[ ]+6ae:[ 	]+fd cb 08 0f[ 	]+rrc $iy\+8$,a
>+[ ]+6b2:[ 	]+fd cb 08 08[ 	]+rrc $iy\+8$,b
>+[ ]+6b6:[ 	]+fd cb 08 09[ 	]+rrc $iy\+8$,c
>+[ ]+6ba:[ 	]+fd cb 08 0a[ 	]+rrc $iy\+8$,d
>+[ ]+6be:[ 	]+fd cb 08 0b[ 	]+rrc $iy\+8$,e
>+[ ]+6c2:[ 	]+fd cb 08 0c[ 	]+rrc $iy\+8$,h
>+[ ]+6c6:[ 	]+fd cb 08 0d[ 	]+rrc $iy\+8$,l
>+[ ]+6ca:[ 	]+dd cb 08 17[ 	]+rl $ix\+8$,a
>+[ ]+6ce:[ 	]+dd cb 08 10[ 	]+rl $ix\+8$,b
>+[ ]+6d2:[ 	]+dd cb 08 11[ 	]+rl $ix\+8$,c
>+[ ]+6d6:[ 	]+dd cb 08 12[ 	]+rl $ix\+8$,d
>+[ ]+6da:[ 	]+dd cb 08 13[ 	]+rl $ix\+8$,e
>+[ ]+6de:[ 	]+dd cb 08 14[ 	]+rl $ix\+8$,h
>+[ ]+6e2:[ 	]+dd cb 08 15[ 	]+rl $ix\+8$,l
>+[ ]+6e6:[ 	]+fd cb 08 17[ 	]+rl $iy\+8$,a
>+[ ]+6ea:[ 	]+fd cb 08 10[ 	]+rl $iy\+8$,b
>+[ ]+6ee:[ 	]+fd cb 08 11[ 	]+rl $iy\+8$,c
>+[ ]+6f2:[ 	]+fd cb 08 12[ 	]+rl $iy\+8$,d
>+[ ]+6f6:[ 	]+fd cb 08 13[ 	]+rl $iy\+8$,e
>+[ ]+6fa:[ 	]+fd cb 08 14[ 	]+rl $iy\+8$,h
>+[ ]+6fe:[ 	]+fd cb 08 15[ 	]+rl $iy\+8$,l
>+[ ]+702:[ 	]+dd cb 08 1f[ 	]+rr $ix\+8$,a
>+[ ]+706:[ 	]+dd cb 08 18[ 	]+rr $ix\+8$,b
>+[ ]+70a:[ 	]+dd cb 08 19[ 	]+rr $ix\+8$,c
>+[ ]+70e:[ 	]+dd cb 08 1a[ 	]+rr $ix\+8$,d
>+[ ]+712:[ 	]+dd cb 08 1b[ 	]+rr $ix\+8$,e
>+[ ]+716:[ 	]+dd cb 08 1c[ 	]+rr $ix\+8$,h
>+[ ]+71a:[ 	]+dd cb 08 1d[ 	]+rr $ix\+8$,l
>+[ ]+71e:[ 	]+fd cb 08 1f[ 	]+rr $iy\+8$,a
>+[ ]+722:[ 	]+fd cb 08 18[ 	]+rr $iy\+8$,b
>+[ ]+726:[ 	]+fd cb 08 19[ 	]+rr $iy\+8$,c
>+[ ]+72a:[ 	]+fd cb 08 1a[ 	]+rr $iy\+8$,d
>+[ ]+72e:[ 	]+fd cb 08 1b[ 	]+rr $iy\+8$,e
>+[ ]+732:[ 	]+fd cb 08 1c[ 	]+rr $iy\+8$,h
>+[ ]+736:[ 	]+fd cb 08 1d[ 	]+rr $iy\+8$,l
>+[ ]+73a:[ 	]+dd cb 08 27[ 	]+sla $ix\+8$,a
>+[ ]+73e:[ 	]+dd cb 08 20[ 	]+sla $ix\+8$,b
>+[ ]+742:[ 	]+dd cb 08 21[ 	]+sla $ix\+8$,c
>+[ ]+746:[ 	]+dd cb 08 22[ 	]+sla $ix\+8$,d
>+[ ]+74a:[ 	]+dd cb 08 23[ 	]+sla $ix\+8$,e
>+[ ]+74e:[ 	]+dd cb 08 24[ 	]+sla $ix\+8$,h
>+[ ]+752:[ 	]+dd cb 08 25[ 	]+sla $ix\+8$,l
>+[ ]+756:[ 	]+fd cb 08 27[ 	]+sla $iy\+8$,a
>+[ ]+75a:[ 	]+fd cb 08 20[ 	]+sla $iy\+8$,b
>+[ ]+75e:[ 	]+fd cb 08 21[ 	]+sla $iy\+8$,c
>+[ ]+762:[ 	]+fd cb 08 22[ 	]+sla $iy\+8$,d
>+[ ]+766:[ 	]+fd cb 08 23[ 	]+sla $iy\+8$,e
>+[ ]+76a:[ 	]+fd cb 08 24[ 	]+sla $iy\+8$,h
>+[ ]+76e:[ 	]+fd cb 08 25[ 	]+sla $iy\+8$,l
>+[ ]+772:[ 	]+dd cb 08 2f[ 	]+sra $ix\+8$,a
>+[ ]+776:[ 	]+dd cb 08 28[ 	]+sra $ix\+8$,b
>+[ ]+77a:[ 	]+dd cb 08 29[ 	]+sra $ix\+8$,c
>+[ ]+77e:[ 	]+dd cb 08 2a[ 	]+sra $ix\+8$,d
>+[ ]+782:[ 	]+dd cb 08 2b[ 	]+sra $ix\+8$,e
>+[ ]+786:[ 	]+dd cb 08 2c[ 	]+sra $ix\+8$,h
>+[ ]+78a:[ 	]+dd cb 08 2d[ 	]+sra $ix\+8$,l
>+[ ]+78e:[ 	]+fd cb 08 2f[ 	]+sra $iy\+8$,a
>+[ ]+792:[ 	]+fd cb 08 28[ 	]+sra $iy\+8$,b
>+[ ]+796:[ 	]+fd cb 08 29[ 	]+sra $iy\+8$,c
>+[ ]+79a:[ 	]+fd cb 08 2a[ 	]+sra $iy\+8$,d
>+[ ]+79e:[ 	]+fd cb 08 2b[ 	]+sra $iy\+8$,e
>+[ ]+7a2:[ 	]+fd cb 08 2c[ 	]+sra $iy\+8$,h
>+[ ]+7a6:[ 	]+fd cb 08 2d[ 	]+sra $iy\+8$,l
>+[ ]+7aa:[ 	]+dd cb 08 37[ 	]+sli $ix\+8$,a
>+[ ]+7ae:[ 	]+dd cb 08 30[ 	]+sli $ix\+8$,b
>+[ ]+7b2:[ 	]+dd cb 08 31[ 	]+sli $ix\+8$,c
>+[ ]+7b6:[ 	]+dd cb 08 32[ 	]+sli $ix\+8$,d
>+[ ]+7ba:[ 	]+dd cb 08 33[ 	]+sli $ix\+8$,e
>+[ ]+7be:[ 	]+dd cb 08 34[ 	]+sli $ix\+8$,h
>+[ ]+7c2:[ 	]+dd cb 08 35[ 	]+sli $ix\+8$,l
>+[ ]+7c6:[ 	]+fd cb 08 37[ 	]+sli $iy\+8$,a
>+[ ]+7ca:[ 	]+fd cb 08 30[ 	]+sli $iy\+8$,b
>+[ ]+7ce:[ 	]+fd cb 08 31[ 	]+sli $iy\+8$,c
>+[ ]+7d2:[ 	]+fd cb 08 32[ 	]+sli $iy\+8$,d
>+[ ]+7d6:[ 	]+fd cb 08 33[ 	]+sli $iy\+8$,e
>+[ ]+7da:[ 	]+fd cb 08 34[ 	]+sli $iy\+8$,h
>+[ ]+7de:[ 	]+fd cb 08 35[ 	]+sli $iy\+8$,l
>+[ ]+7e2:[ 	]+dd cb 08 3f[ 	]+srl $ix\+8$,a
>+[ ]+7e6:[ 	]+dd cb 08 38[ 	]+srl $ix\+8$,b
>+[ ]+7ea:[ 	]+dd cb 08 39[ 	]+srl $ix\+8$,c
>+[ ]+7ee:[ 	]+dd cb 08 3a[ 	]+srl $ix\+8$,d
>+[ ]+7f2:[ 	]+dd cb 08 3b[ 	]+srl $ix\+8$,e
>+[ ]+7f6:[ 	]+dd cb 08 3c[ 	]+srl $ix\+8$,h
>+[ ]+7fa:[ 	]+dd cb 08 3d[ 	]+srl $ix\+8$,l
>+[ ]+7fe:[ 	]+fd cb 08 3f[ 	]+srl $iy\+8$,a
>+[ ]+802:[ 	]+fd cb 08 38[ 	]+srl $iy\+8$,b
>+[ ]+806:[ 	]+fd cb 08 39[ 	]+srl $iy\+8$,c
>+[ ]+80a:[ 	]+fd cb 08 3a[ 	]+srl $iy\+8$,d
>+[ ]+80e:[ 	]+fd cb 08 3b[ 	]+srl $iy\+8$,e
>+[ ]+812:[ 	]+fd cb 08 3c[ 	]+srl $iy\+8$,h
>+[ ]+816:[ 	]+fd cb 08 3d[ 	]+srl $iy\+8$,l
>+[ ]+81a:[ 	]+dd cb 08 87[ 	]+res 0,$ix\+8$,a
>+[ ]+81e:[ 	]+dd cb 08 80[ 	]+res 0,$ix\+8$,b
>+[ ]+822:[ 	]+dd cb 08 81[ 	]+res 0,$ix\+8$,c
>+[ ]+826:[ 	]+dd cb 08 82[ 	]+res 0,$ix\+8$,d
>+[ ]+82a:[ 	]+dd cb 08 83[ 	]+res 0,$ix\+8$,e
>+[ ]+82e:[ 	]+dd cb 08 84[ 	]+res 0,$ix\+8$,h
>+[ ]+832:[ 	]+dd cb 08 85[ 	]+res 0,$ix\+8$,l
>+[ ]+836:[ 	]+fd cb 08 87[ 	]+res 0,$iy\+8$,a
>+[ ]+83a:[ 	]+fd cb 08 80[ 	]+res 0,$iy\+8$,b
>+[ ]+83e:[ 	]+fd cb 08 81[ 	]+res 0,$iy\+8$,c
>+[ ]+842:[ 	]+fd cb 08 82[ 	]+res 0,$iy\+8$,d
>+[ ]+846:[ 	]+fd cb 08 83[ 	]+res 0,$iy\+8$,e
>+[ ]+84a:[ 	]+fd cb 08 84[ 	]+res 0,$iy\+8$,h
>+[ ]+84e:[ 	]+fd cb 08 85[ 	]+res 0,$iy\+8$,l
>+[ ]+852:[ 	]+dd cb 08 8f[ 	]+res 1,$ix\+8$,a
>+[ ]+856:[ 	]+dd cb 08 88[ 	]+res 1,$ix\+8$,b
>+[ ]+85a:[ 	]+dd cb 08 89[ 	]+res 1,$ix\+8$,c
>+[ ]+85e:[ 	]+dd cb 08 8a[ 	]+res 1,$ix\+8$,d
>+[ ]+862:[ 	]+dd cb 08 8b[ 	]+res 1,$ix\+8$,e
>+[ ]+866:[ 	]+dd cb 08 8c[ 	]+res 1,$ix\+8$,h
>+[ ]+86a:[ 	]+dd cb 08 8d[ 	]+res 1,$ix\+8$,l
>+[ ]+86e:[ 	]+fd cb 08 8f[ 	]+res 1,$iy\+8$,a
>+[ ]+872:[ 	]+fd cb 08 88[ 	]+res 1,$iy\+8$,b
>+[ ]+876:[ 	]+fd cb 08 89[ 	]+res 1,$iy\+8$,c
>+[ ]+87a:[ 	]+fd cb 08 8a[ 	]+res 1,$iy\+8$,d
>+[ ]+87e:[ 	]+fd cb 08 8b[ 	]+res 1,$iy\+8$,e
>+[ ]+882:[ 	]+fd cb 08 8c[ 	]+res 1,$iy\+8$,h
>+[ ]+886:[ 	]+fd cb 08 8d[ 	]+res 1,$iy\+8$,l
>+[ ]+88a:[ 	]+dd cb 08 97[ 	]+res 2,$ix\+8$,a
>+[ ]+88e:[ 	]+dd cb 08 90[ 	]+res 2,$ix\+8$,b
>+[ ]+892:[ 	]+dd cb 08 91[ 	]+res 2,$ix\+8$,c
>+[ ]+896:[ 	]+dd cb 08 92[ 	]+res 2,$ix\+8$,d
>+[ ]+89a:[ 	]+dd cb 08 93[ 	]+res 2,$ix\+8$,e
>+[ ]+89e:[ 	]+dd cb 08 94[ 	]+res 2,$ix\+8$,h
>+[ ]+8a2:[ 	]+dd cb 08 95[ 	]+res 2,$ix\+8$,l
>+[ ]+8a6:[ 	]+fd cb 08 97[ 	]+res 2,$iy\+8$,a
>+[ ]+8aa:[ 	]+fd cb 08 90[ 	]+res 2,$iy\+8$,b
>+[ ]+8ae:[ 	]+fd cb 08 91[ 	]+res 2,$iy\+8$,c
>+[ ]+8b2:[ 	]+fd cb 08 92[ 	]+res 2,$iy\+8$,d
>+[ ]+8b6:[ 	]+fd cb 08 93[ 	]+res 2,$iy\+8$,e
>+[ ]+8ba:[ 	]+fd cb 08 94[ 	]+res 2,$iy\+8$,h
>+[ ]+8be:[ 	]+fd cb 08 95[ 	]+res 2,$iy\+8$,l
>+[ ]+8c2:[ 	]+dd cb 08 9f[ 	]+res 3,$ix\+8$,a
>+[ ]+8c6:[ 	]+dd cb 08 98[ 	]+res 3,$ix\+8$,b
>+[ ]+8ca:[ 	]+dd cb 08 99[ 	]+res 3,$ix\+8$,c
>+[ ]+8ce:[ 	]+dd cb 08 9a[ 	]+res 3,$ix\+8$,d
>+[ ]+8d2:[ 	]+dd cb 08 9b[ 	]+res 3,$ix\+8$,e
>+[ ]+8d6:[ 	]+dd cb 08 9c[ 	]+res 3,$ix\+8$,h
>+[ ]+8da:[ 	]+dd cb 08 9d[ 	]+res 3,$ix\+8$,l
>+[ ]+8de:[ 	]+fd cb 08 9f[ 	]+res 3,$iy\+8$,a
>+[ ]+8e2:[ 	]+fd cb 08 98[ 	]+res 3,$iy\+8$,b
>+[ ]+8e6:[ 	]+fd cb 08 99[ 	]+res 3,$iy\+8$,c
>+[ ]+8ea:[ 	]+fd cb 08 9a[ 	]+res 3,$iy\+8$,d
>+[ ]+8ee:[ 	]+fd cb 08 9b[ 	]+res 3,$iy\+8$,e
>+[ ]+8f2:[ 	]+fd cb 08 9c[ 	]+res 3,$iy\+8$,h
>+[ ]+8f6:[ 	]+fd cb 08 9d[ 	]+res 3,$iy\+8$,l
>+[ ]+8fa:[ 	]+dd cb 08 a7[ 	]+res 4,$ix\+8$,a
>+[ ]+8fe:[ 	]+dd cb 08 a0[ 	]+res 4,$ix\+8$,b
>+[ ]+902:[ 	]+dd cb 08 a1[ 	]+res 4,$ix\+8$,c
>+[ ]+906:[ 	]+dd cb 08 a2[ 	]+res 4,$ix\+8$,d
>+[ ]+90a:[ 	]+dd cb 08 a3[ 	]+res 4,$ix\+8$,e
>+[ ]+90e:[ 	]+dd cb 08 a4[ 	]+res 4,$ix\+8$,h
>+[ ]+912:[ 	]+dd cb 08 a5[ 	]+res 4,$ix\+8$,l
>+[ ]+916:[ 	]+fd cb 08 a7[ 	]+res 4,$iy\+8$,a
>+[ ]+91a:[ 	]+fd cb 08 a0[ 	]+res 4,$iy\+8$,b
>+[ ]+91e:[ 	]+fd cb 08 a1[ 	]+res 4,$iy\+8$,c
>+[ ]+922:[ 	]+fd cb 08 a2[ 	]+res 4,$iy\+8$,d
>+[ ]+926:[ 	]+fd cb 08 a3[ 	]+res 4,$iy\+8$,e
>+[ ]+92a:[ 	]+fd cb 08 a4[ 	]+res 4,$iy\+8$,h
>+[ ]+92e:[ 	]+fd cb 08 a5[ 	]+res 4,$iy\+8$,l
>+[ ]+932:[ 	]+dd cb 08 af[ 	]+res 5,$ix\+8$,a
>+[ ]+936:[ 	]+dd cb 08 a8[ 	]+res 5,$ix\+8$,b
>+[ ]+93a:[ 	]+dd cb 08 a9[ 	]+res 5,$ix\+8$,c
>+[ ]+93e:[ 	]+dd cb 08 aa[ 	]+res 5,$ix\+8$,d
>+[ ]+942:[ 	]+dd cb 08 ab[ 	]+res 5,$ix\+8$,e
>+[ ]+946:[ 	]+dd cb 08 ac[ 	]+res 5,$ix\+8$,h
>+[ ]+94a:[ 	]+dd cb 08 ad[ 	]+res 5,$ix\+8$,l
>+[ ]+94e:[ 	]+fd cb 08 af[ 	]+res 5,$iy\+8$,a
>+[ ]+952:[ 	]+fd cb 08 a8[ 	]+res 5,$iy\+8$,b
>+[ ]+956:[ 	]+fd cb 08 a9[ 	]+res 5,$iy\+8$,c
>+[ ]+95a:[ 	]+fd cb 08 aa[ 	]+res 5,$iy\+8$,d
>+[ ]+95e:[ 	]+fd cb 08 ab[ 	]+res 5,$iy\+8$,e
>+[ ]+962:[ 	]+fd cb 08 ac[ 	]+res 5,$iy\+8$,h
>+[ ]+966:[ 	]+fd cb 08 ad[ 	]+res 5,$iy\+8$,l
>+[ ]+96a:[ 	]+dd cb 08 b7[ 	]+res 6,$ix\+8$,a
>+[ ]+96e:[ 	]+dd cb 08 b0[ 	]+res 6,$ix\+8$,b
>+[ ]+972:[ 	]+dd cb 08 b1[ 	]+res 6,$ix\+8$,c
>+[ ]+976:[ 	]+dd cb 08 b2[ 	]+res 6,$ix\+8$,d
>+[ ]+97a:[ 	]+dd cb 08 b3[ 	]+res 6,$ix\+8$,e
>+[ ]+97e:[ 	]+dd cb 08 b4[ 	]+res 6,$ix\+8$,h
>+[ ]+982:[ 	]+dd cb 08 b5[ 	]+res 6,$ix\+8$,l
>+[ ]+986:[ 	]+fd cb 08 b7[ 	]+res 6,$iy\+8$,a
>+[ ]+98a:[ 	]+fd cb 08 b0[ 	]+res 6,$iy\+8$,b
>+[ ]+98e:[ 	]+fd cb 08 b1[ 	]+res 6,$iy\+8$,c
>+[ ]+992:[ 	]+fd cb 08 b2[ 	]+res 6,$iy\+8$,d
>+[ ]+996:[ 	]+fd cb 08 b3[ 	]+res 6,$iy\+8$,e
>+[ ]+99a:[ 	]+fd cb 08 b4[ 	]+res 6,$iy\+8$,h
>+[ ]+99e:[ 	]+fd cb 08 b5[ 	]+res 6,$iy\+8$,l
>+[ ]+9a2:[ 	]+dd cb 08 bf[ 	]+res 7,$ix\+8$,a
>+[ ]+9a6:[ 	]+dd cb 08 b8[ 	]+res 7,$ix\+8$,b
>+[ ]+9aa:[ 	]+dd cb 08 b9[ 	]+res 7,$ix\+8$,c
>+[ ]+9ae:[ 	]+dd cb 08 ba[ 	]+res 7,$ix\+8$,d
>+[ ]+9b2:[ 	]+dd cb 08 bb[ 	]+res 7,$ix\+8$,e
>+[ ]+9b6:[ 	]+dd cb 08 bc[ 	]+res 7,$ix\+8$,h
>+[ ]+9ba:[ 	]+dd cb 08 bd[ 	]+res 7,$ix\+8$,l
>+[ ]+9be:[ 	]+fd cb 08 bf[ 	]+res 7,$iy\+8$,a
>+[ ]+9c2:[ 	]+fd cb 08 b8[ 	]+res 7,$iy\+8$,b
>+[ ]+9c6:[ 	]+fd cb 08 b9[ 	]+res 7,$iy\+8$,c
>+[ ]+9ca:[ 	]+fd cb 08 ba[ 	]+res 7,$iy\+8$,d
>+[ ]+9ce:[ 	]+fd cb 08 bb[ 	]+res 7,$iy\+8$,e
>+[ ]+9d2:[ 	]+fd cb 08 bc[ 	]+res 7,$iy\+8$,h
>+[ ]+9d6:[ 	]+fd cb 08 bd[ 	]+res 7,$iy\+8$,l
>+[ ]+9da:[ 	]+dd cb 08 c7[ 	]+set 0,$ix\+8$,a
>+[ ]+9de:[ 	]+dd cb 08 c0[ 	]+set 0,$ix\+8$,b
>+[ ]+9e2:[ 	]+dd cb 08 c1[ 	]+set 0,$ix\+8$,c
>+[ ]+9e6:[ 	]+dd cb 08 c2[ 	]+set 0,$ix\+8$,d
>+[ ]+9ea:[ 	]+dd cb 08 c3[ 	]+set 0,$ix\+8$,e
>+[ ]+9ee:[ 	]+dd cb 08 c4[ 	]+set 0,$ix\+8$,h
>+[ ]+9f2:[ 	]+dd cb 08 c5[ 	]+set 0,$ix\+8$,l
>+[ ]+9f6:[ 	]+fd cb 08 c7[ 	]+set 0,$iy\+8$,a
>+[ ]+9fa:[ 	]+fd cb 08 c0[ 	]+set 0,$iy\+8$,b
>+[ ]+9fe:[ 	]+fd cb 08 c1[ 	]+set 0,$iy\+8$,c
>+[ ]+a02:[ 	]+fd cb 08 c2[ 	]+set 0,$iy\+8$,d
>+[ ]+a06:[ 	]+fd cb 08 c3[ 	]+set 0,$iy\+8$,e
>+[ ]+a0a:[ 	]+fd cb 08 c4[ 	]+set 0,$iy\+8$,h
>+[ ]+a0e:[ 	]+fd cb 08 c5[ 	]+set 0,$iy\+8$,l
>+[ ]+a12:[ 	]+dd cb 08 cf[ 	]+set 1,$ix\+8$,a
>+[ ]+a16:[ 	]+dd cb 08 c8[ 	]+set 1,$ix\+8$,b
>+[ ]+a1a:[ 	]+dd cb 08 c9[ 	]+set 1,$ix\+8$,c
>+[ ]+a1e:[ 	]+dd cb 08 ca[ 	]+set 1,$ix\+8$,d
>+[ ]+a22:[ 	]+dd cb 08 cb[ 	]+set 1,$ix\+8$,e
>+[ ]+a26:[ 	]+dd cb 08 cc[ 	]+set 1,$ix\+8$,h
>+[ ]+a2a:[ 	]+dd cb 08 cd[ 	]+set 1,$ix\+8$,l
>+[ ]+a2e:[ 	]+fd cb 08 cf[ 	]+set 1,$iy\+8$,a
>+[ ]+a32:[ 	]+fd cb 08 c8[ 	]+set 1,$iy\+8$,b
>+[ ]+a36:[ 	]+fd cb 08 c9[ 	]+set 1,$iy\+8$,c
>+[ ]+a3a:[ 	]+fd cb 08 ca[ 	]+set 1,$iy\+8$,d
>+[ ]+a3e:[ 	]+fd cb 08 cb[ 	]+set 1,$iy\+8$,e
>+[ ]+a42:[ 	]+fd cb 08 cc[ 	]+set 1,$iy\+8$,h
>+[ ]+a46:[ 	]+fd cb 08 cd[ 	]+set 1,$iy\+8$,l
>+[ ]+a4a:[ 	]+dd cb 08 d7[ 	]+set 2,$ix\+8$,a
>+[ ]+a4e:[ 	]+dd cb 08 d0[ 	]+set 2,$ix\+8$,b
>+[ ]+a52:[ 	]+dd cb 08 d1[ 	]+set 2,$ix\+8$,c
>+[ ]+a56:[ 	]+dd cb 08 d2[ 	]+set 2,$ix\+8$,d
>+[ ]+a5a:[ 	]+dd cb 08 d3[ 	]+set 2,$ix\+8$,e
>+[ ]+a5e:[ 	]+dd cb 08 d4[ 	]+set 2,$ix\+8$,h
>+[ ]+a62:[ 	]+dd cb 08 d5[ 	]+set 2,$ix\+8$,l
>+[ ]+a66:[ 	]+fd cb 08 d7[ 	]+set 2,$iy\+8$,a
>+[ ]+a6a:[ 	]+fd cb 08 d0[ 	]+set 2,$iy\+8$,b
>+[ ]+a6e:[ 	]+fd cb 08 d1[ 	]+set 2,$iy\+8$,c
>+[ ]+a72:[ 	]+fd cb 08 d2[ 	]+set 2,$iy\+8$,d
>+[ ]+a76:[ 	]+fd cb 08 d3[ 	]+set 2,$iy\+8$,e
>+[ ]+a7a:[ 	]+fd cb 08 d4[ 	]+set 2,$iy\+8$,h
>+[ ]+a7e:[ 	]+fd cb 08 d5[ 	]+set 2,$iy\+8$,l
>+[ ]+a82:[ 	]+dd cb 08 df[ 	]+set 3,$ix\+8$,a
>+[ ]+a86:[ 	]+dd cb 08 d8[ 	]+set 3,$ix\+8$,b
>+[ ]+a8a:[ 	]+dd cb 08 d9[ 	]+set 3,$ix\+8$,c
>+[ ]+a8e:[ 	]+dd cb 08 da[ 	]+set 3,$ix\+8$,d
>+[ ]+a92:[ 	]+dd cb 08 db[ 	]+set 3,$ix\+8$,e
>+[ ]+a96:[ 	]+dd cb 08 dc[ 	]+set 3,$ix\+8$,h
>+[ ]+a9a:[ 	]+dd cb 08 dd[ 	]+set 3,$ix\+8$,l
>+[ ]+a9e:[ 	]+fd cb 08 df[ 	]+set 3,$iy\+8$,a
>+[ ]+aa2:[ 	]+fd cb 08 d8[ 	]+set 3,$iy\+8$,b
>+[ ]+aa6:[ 	]+fd cb 08 d9[ 	]+set 3,$iy\+8$,c
>+[ ]+aaa:[ 	]+fd cb 08 da[ 	]+set 3,$iy\+8$,d
>+[ ]+aae:[ 	]+fd cb 08 db[ 	]+set 3,$iy\+8$,e
>+[ ]+ab2:[ 	]+fd cb 08 dc[ 	]+set 3,$iy\+8$,h
>+[ ]+ab6:[ 	]+fd cb 08 dd[ 	]+set 3,$iy\+8$,l
>+[ ]+aba:[ 	]+dd cb 08 e7[ 	]+set 4,$ix\+8$,a
>+[ ]+abe:[ 	]+dd cb 08 e0[ 	]+set 4,$ix\+8$,b
>+[ ]+ac2:[ 	]+dd cb 08 e1[ 	]+set 4,$ix\+8$,c
>+[ ]+ac6:[ 	]+dd cb 08 e2[ 	]+set 4,$ix\+8$,d
>+[ ]+aca:[ 	]+dd cb 08 e3[ 	]+set 4,$ix\+8$,e
>+[ ]+ace:[ 	]+dd cb 08 e4[ 	]+set 4,$ix\+8$,h
>+[ ]+ad2:[ 	]+dd cb 08 e5[ 	]+set 4,$ix\+8$,l
>+[ ]+ad6:[ 	]+fd cb 08 e7[ 	]+set 4,$iy\+8$,a
>+[ ]+ada:[ 	]+fd cb 08 e0[ 	]+set 4,$iy\+8$,b
>+[ ]+ade:[ 	]+fd cb 08 e1[ 	]+set 4,$iy\+8$,c
>+[ ]+ae2:[ 	]+fd cb 08 e2[ 	]+set 4,$iy\+8$,d
>+[ ]+ae6:[ 	]+fd cb 08 e3[ 	]+set 4,$iy\+8$,e
>+[ ]+aea:[ 	]+fd cb 08 e4[ 	]+set 4,$iy\+8$,h
>+[ ]+aee:[ 	]+fd cb 08 e5[ 	]+set 4,$iy\+8$,l
>+[ ]+af2:[ 	]+dd cb 08 ef[ 	]+set 5,$ix\+8$,a
>+[ ]+af6:[ 	]+dd cb 08 e8[ 	]+set 5,$ix\+8$,b
>+[ ]+afa:[ 	]+dd cb 08 e9[ 	]+set 5,$ix\+8$,c
>+[ ]+afe:[ 	]+dd cb 08 ea[ 	]+set 5,$ix\+8$,d
>+[ ]+b02:[ 	]+dd cb 08 eb[ 	]+set 5,$ix\+8$,e
>+[ ]+b06:[ 	]+dd cb 08 ec[ 	]+set 5,$ix\+8$,h
>+[ ]+b0a:[ 	]+dd cb 08 ed[ 	]+set 5,$ix\+8$,l
>+[ ]+b0e:[ 	]+fd cb 08 ef[ 	]+set 5,$iy\+8$,a
>+[ ]+b12:[ 	]+fd cb 08 e8[ 	]+set 5,$iy\+8$,b
>+[ ]+b16:[ 	]+fd cb 08 e9[ 	]+set 5,$iy\+8$,c
>+[ ]+b1a:[ 	]+fd cb 08 ea[ 	]+set 5,$iy\+8$,d
>+[ ]+b1e:[ 	]+fd cb 08 eb[ 	]+set 5,$iy\+8$,e
>+[ ]+b22:[ 	]+fd cb 08 ec[ 	]+set 5,$iy\+8$,h
>+[ ]+b26:[ 	]+fd cb 08 ed[ 	]+set 5,$iy\+8$,l
>+[ ]+b2a:[ 	]+dd cb 08 f7[ 	]+set 6,$ix\+8$,a
>+[ ]+b2e:[ 	]+dd cb 08 f0[ 	]+set 6,$ix\+8$,b
>+[ ]+b32:[ 	]+dd cb 08 f1[ 	]+set 6,$ix\+8$,c
>+[ ]+b36:[ 	]+dd cb 08 f2[ 	]+set 6,$ix\+8$,d
>+[ ]+b3a:[ 	]+dd cb 08 f3[ 	]+set 6,$ix\+8$,e
>+[ ]+b3e:[ 	]+dd cb 08 f4[ 	]+set 6,$ix\+8$,h
>+[ ]+b42:[ 	]+dd cb 08 f5[ 	]+set 6,$ix\+8$,l
>+[ ]+b46:[ 	]+fd cb 08 f7[ 	]+set 6,$iy\+8$,a
>+[ ]+b4a:[ 	]+fd cb 08 f0[ 	]+set 6,$iy\+8$,b
>+[ ]+b4e:[ 	]+fd cb 08 f1[ 	]+set 6,$iy\+8$,c
>+[ ]+b52:[ 	]+fd cb 08 f2[ 	]+set 6,$iy\+8$,d
>+[ ]+b56:[ 	]+fd cb 08 f3[ 	]+set 6,$iy\+8$,e
>+[ ]+b5a:[ 	]+fd cb 08 f4[ 	]+set 6,$iy\+8$,h
>+[ ]+b5e:[ 	]+fd cb 08 f5[ 	]+set 6,$iy\+8$,l
>+[ ]+b62:[ 	]+dd cb 08 ff[ 	]+set 7,$ix\+8$,a
>+[ ]+b66:[ 	]+dd cb 08 f8[ 	]+set 7,$ix\+8$,b
>+[ ]+b6a:[ 	]+dd cb 08 f9[ 	]+set 7,$ix\+8$,c
>+[ ]+b6e:[ 	]+dd cb 08 fa[ 	]+set 7,$ix\+8$,d
>+[ ]+b72:[ 	]+dd cb 08 fb[ 	]+set 7,$ix\+8$,e
>+[ ]+b76:[ 	]+dd cb 08 fc[ 	]+set 7,$ix\+8$,h
>+[ ]+b7a:[ 	]+dd cb 08 fd[ 	]+set 7,$ix\+8$,l
>+[ ]+b7e:[ 	]+fd cb 08 ff[ 	]+set 7,$iy\+8$,a
>+[ ]+b82:[ 	]+fd cb 08 f8[ 	]+set 7,$iy\+8$,b
>+[ ]+b86:[ 	]+fd cb 08 f9[ 	]+set 7,$iy\+8$,c
>+[ ]+b8a:[ 	]+fd cb 08 fa[ 	]+set 7,$iy\+8$,d
>+[ ]+b8e:[ 	]+fd cb 08 fb[ 	]+set 7,$iy\+8$,e
>+[ ]+b92:[ 	]+fd cb 08 fc[ 	]+set 7,$iy\+8$,h
>+[ ]+b96:[ 	]+fd cb 08 fd[ 	]+set 7,$iy\+8$,l
>+[ ]+b9a:[ 	]+cb 37[       	]+sli a
>+[ ]+b9c:[ 	]+cb 30[       	]+sli b
>+[ ]+b9e:[ 	]+cb 31[       	]+sli c
>+[ ]+ba0:[ 	]+cb 32[       	]+sli d
>+[ ]+ba2:[ 	]+cb 33[       	]+sli e
>+[ ]+ba4:[ 	]+cb 34[       	]+sli h
>+[ ]+ba6:[ 	]+cb 35[       	]+sli l
>+[ ]+ba8:[ 	]+cb 36[       	]+sli $hl$
>+[ ]+baa:[ 	]+dd cb 07 36[ 	]+sli $ix\+7$
>+[ ]+bae:[ 	]+fd cb f7 36[ 	]+sli $iy\-9$
>+[ ]+bb2:[ 	]+cb 37[       	]+sli a
>+[ ]+bb4:[ 	]+cb 30[       	]+sli b
>+[ ]+bb6:[ 	]+cb 31[       	]+sli c
>+[ ]+bb8:[ 	]+cb 32[       	]+sli d
>+[ ]+bba:[ 	]+cb 33[       	]+sli e
>+[ ]+bbc:[ 	]+cb 34[       	]+sli h
>+[ ]+bbe:[ 	]+cb 35[       	]+sli l
>+[ ]+bc0:[ 	]+cb 36[       	]+sli $hl$
>+[ ]+bc2:[ 	]+dd cb 07 36[ 	]+sli $ix\+7$
>+[ ]+bc6:[ 	]+fd cb f7 36[ 	]+sli $iy\-9$
>+[ ]+bca:[ 	]+cb 37[       	]+sli a
>+[ ]+bcc:[ 	]+cb 30[       	]+sli b
>+[ ]+bce:[ 	]+cb 31[       	]+sli c
>+[ ]+bd0:[ 	]+cb 32[       	]+sli d
>+[ ]+bd2:[ 	]+cb 33[       	]+sli e
>+[ ]+bd4:[ 	]+cb 34[       	]+sli h
>+[ ]+bd6:[ 	]+cb 35[       	]+sli l
>+[ ]+bd8:[ 	]+cb 36[       	]+sli $hl$
>+[ ]+bda:[ 	]+dd cb 07 36[ 	]+sli $ix\+7$
>+[ ]+bde:[ 	]+fd cb f7 36[ 	]+sli $iy\-9$
>+[ ]+be2:[ 	]+ed a4[       	]+ldix
>+[ ]+be4:[ 	]+ed a5[       	]+ldws
>+[ ]+be6:[ 	]+ed b4[       	]+ldirx
>+[ ]+be8:[ 	]+ed ac[       	]+lddx
>+[ ]+bea:[ 	]+ed bc[       	]+lddrx
>+[ ]+bec:[ 	]+ed b7[       	]+ldpirx
>+[ ]+bee:[ 	]+ed 90[       	]+outinb
>+[ ]+bf0:[ 	]+ed 30[       	]+mul d,e
>+[ ]+bf2:[ 	]+ed 31[       	]+add hl,a
>+[ ]+bf4:[ 	]+ed 32[       	]+add de,a
>+[ ]+bf6:[ 	]+ed 33[       	]+add bc,a
>+[ ]+bf8:[ 	]+ed 34 af be[ 	]+add hl,0xbeaf
>+[ ]+bfc:[ 	]+ed 35 ad de[ 	]+add de,0xdead
>+[ ]+c00:[ 	]+ed 36 34 12[ 	]+add bc,0x1234
>+[ ]+c04:[ 	]+ed 23[       	]+swapnib
>+[ ]+c06:[ 	]+ed 24[       	]+mirror
>+[ ]+c08:[ 	]+ed 8a 12 34[ 	]+push 0x1234
>+[ ]+c0c:[ 	]+ed 91 12 34[ 	]+nextreg 0x12,0x34
>+[ ]+c10:[ 	]+ed 92 56[    	]+nextreg 0x56,a
>+[ ]+c13:[ 	]+ed 93[       	]+pixeldn
>+[ ]+c15:[ 	]+ed 94[       	]+pixelad
>+[ ]+c17:[ 	]+ed 95[       	]+setae
>+[ ]+c19:[ 	]+ed 27 78[    	]+test 0x78
>+[ ]+c1c:[ 	]+ed 28[       	]+bsla de,b
>+[ ]+c1e:[ 	]+ed 29[       	]+bsra de,b
>+[ ]+c20:[ 	]+ed 2a[       	]+bsrl de,b
>+[ ]+c22:[ 	]+ed 2b[       	]+bsrf de,b
>+[ ]+c24:[ 	]+ed 2c[       	]+bslc de,b
>+[ ]+c26:[ 	]+ed 98[       	]+jp $c$
>+[ ]+c28:[ 	]+ed 8a 00 00[ 	]+push 0x0000
>+[ ]+c2c:[ 	]+ed 30[       	]+mul d,e
>+[ ]+c2e:[ 	]+ed 23[       	]+swapnib
>+[ ]+c30:[ 	]+ed 27 ab[    	]+test 0xab
>+#pass
>diff --git a/gas/testsuite/gas/z80/z80n_all.s b/gas/testsuite/gas/z80/z80n_all.s
>new file mode 100644
>index 0000000000..3d0e341ecf
>--- /dev/null
>+++ b/gas/testsuite/gas/z80/z80n_all.s
>@@ -0,0 +1,1242 @@
>+	.text
>+	.org	0
>+
>+	adc	a,(hl)
>+	adc	a,(ix+9)
>+	adc	a,(iy+9)
>+	adc	a,3
>+	adc	a,a
>+	adc	a,b
>+	adc	a,c
>+	adc	a,d
>+	adc	a,e
>+	adc	a,h
>+	adc	a,l
>+	adc	hl,bc
>+	adc	hl,de
>+	adc	hl,hl
>+	adc	hl,sp
>+	add	a,(hl)
>+	add	a,(ix+9)
>+	add	a,(iy+9)
>+	add	a,3
>+	add	a,a
>+	add	a,b
>+	add	a,c
>+	add	a,d
>+	add	a,e
>+	add	a,h
>+	add	a,l
>+	add	hl,bc
>+	add	hl,de
>+	add	hl,hl
>+	add	hl,sp
>+	add	ix,bc
>+	add	ix,de
>+	add	ix,ix
>+	add	ix,sp
>+	add	iy,bc
>+	add	iy,de
>+	add	iy,iy
>+	add	iy,sp
>+	and	(hl)
>+	and	(ix+9)
>+	and	(iy+9)
>+	and	3
>+	and	a
>+	and	b
>+	and	c
>+	and	d
>+	and	e
>+	and	h
>+	and	l
>+	bit	0,(hl)
>+	bit	0,(ix+9)
>+	bit	0,(iy+9)
>+	bit	0,a
>+	bit	0,b
>+	bit	0,c
>+	bit	0,d
>+	bit	0,e
>+	bit	0,h
>+	bit	0,l
>+	bit	1,(hl)
>+	bit	1,(ix+9)
>+	bit	1,(iy+9)
>+	bit	1,a
>+	bit	1,b
>+	bit	1,c
>+	bit	1,d
>+	bit	1,e
>+	bit	1,h
>+	bit	1,l
>+	bit	2,(hl)
>+	bit	2,(ix+9)
>+	bit	2,(iy+9)
>+	bit	2,a
>+	bit	2,b
>+	bit	2,c
>+	bit	2,d
>+	bit	2,e
>+	bit	2,h
>+	bit	2,l
>+	bit	3,(hl)
>+	bit	3,(ix+9)
>+	bit	3,(iy+9)
>+	bit	3,a
>+	bit	3,b
>+	bit	3,c
>+	bit	3,d
>+	bit	3,e
>+	bit	3,h
>+	bit	3,l
>+	bit	4,(hl)
>+	bit	4,(ix+9)
>+	bit	4,(iy+9)
>+	bit	4,a
>+	bit	4,b
>+	bit	4,c
>+	bit	4,d
>+	bit	4,e
>+	bit	4,h
>+	bit	4,l
>+	bit	5,(hl)
>+	bit	5,(ix+9)
>+	bit	5,(iy+9)
>+	bit	5,a
>+	bit	5,b
>+	bit	5,c
>+	bit	5,d
>+	bit	5,e
>+	bit	5,h
>+	bit	5,l
>+	bit	6,(hl)
>+	bit	6,(ix+9)
>+	bit	6,(iy+9)
>+	bit	6,a
>+	bit	6,b
>+	bit	6,c
>+	bit	6,d
>+	bit	6,e
>+	bit	6,h
>+	bit	6,l
>+	bit	7,(hl)
>+	bit	7,(ix+9)
>+	bit	7,(iy+9)
>+	bit	7,a
>+	bit	7,b
>+	bit	7,c
>+	bit	7,d
>+	bit	7,e
>+	bit	7,h
>+	bit	7,l
>+	call	0x1234
>+	call	c,0x1234
>+	call	m,0x1234
>+	call	nc,0x1234
>+	call	nz,0x1234
>+	call	p,0x1234
>+	call	pe,0x1234
>+	call	po,0x1234
>+	call	z,0x1234
>+	ccf
>+	cp	(hl)
>+	cp	(ix+9)
>+	cp	(iy+9)
>+	cp	03
>+	cp	a
>+	cp	b
>+	cp	c
>+	cp	d
>+	cp	e
>+	cp	h
>+	cp	l
>+	cpd
>+	cpdr
>+	cpi
>+	cpir
>+	cpl
>+	daa
>+	dec	(hl)
>+	dec	(ix+9)
>+	dec	(iy+9)
>+	dec	a
>+	dec	b
>+	dec	bc
>+	dec	c
>+	dec	d
>+	dec	de
>+	dec	e
>+	dec	h
>+	dec	hl
>+	dec	ix
>+	dec	iy
>+	dec	l
>+	dec	sp
>+	di
>+	djnz	.+7
>+	ei
>+	ex	(sp),hl
>+	ex	(sp),ix
>+	ex	(sp),iy
>+	ex	af,af'	;'
>+	ex	de,hl
>+	exx
>+	halt
>+	im	0
>+	im	1
>+	im	2
>+	in	a,(c)
>+	in	a,(3)
>+	in	b,(c)
>+	in	c,(c)
>+	in	d,(c)
>+	in	e,(c)
>+	in	h,(c)
>+	in	l,(c)
>+	inc	(hl)
>+	inc	(ix+9)
>+	inc	(iy+9)
>+	inc	a
>+	inc	b
>+	inc	bc
>+	inc	c
>+	inc	d
>+	inc	de
>+	inc	e
>+	inc	h
>+	inc	hl
>+	inc	ix
>+	inc	iy
>+	inc	l
>+	inc	sp
>+	ind
>+	indr
>+	ini
>+	inir
>+	jp	(hl)
>+	jp	(ix)
>+	jp	(iy)
>+	jp	0x1234
>+	jp	c,0x1234
>+	jp	m,0x1234
>+	jp	nc,0x1234
>+	jp	nz,0x1234
>+	jp	p,0x1234
>+	jp	pe,0x1234
>+	jp	po,0x1234
>+	jp	z,0x1234
>+	jr	.+7
>+	jr	c,.+7
>+	jr	nc,.+7
>+	jr	nz,.+7
>+	jr	z,.+7
>+	ld	(0x1234),a
>+	ld	(0x1234),bc
>+	ld	(0x1234),de
>+	ld	(0x1234),hl
>+	ld	(0x1234),ix
>+	ld	(0x1234),iy
>+	ld	(0x1234),sp
>+	ld	(bc),a
>+	ld	(de),a
>+	ld	(hl),3
>+	ld	(hl),a
>+	ld	(hl),b
>+	ld	(hl),c
>+	ld	(hl),d
>+	ld	(hl),e
>+	ld	(hl),h
>+	ld	(hl),l
>+	ld	(ix+9),3
>+	ld	(ix+9),a
>+	ld	(ix+9),b
>+	ld	(ix+9),c
>+	ld	(ix+9),d
>+	ld	(ix+9),e
>+	ld	(ix+9),h
>+	ld	(ix+9),l
>+	ld	(iy+9),3
>+	ld	(iy+9),a
>+	ld	(iy+9),b
>+	ld	(iy+9),c
>+	ld	(iy+9),d
>+	ld	(iy+9),e
>+	ld	(iy+9),h
>+	ld	(iy+9),l
>+	ld	a,(0x1234)
>+	ld	a,(bc)
>+	ld	a,(de)
>+	ld	a,(hl)
>+	ld	a,(ix+9)
>+	ld	a,(iy+9)
>+	ld	a,3
>+	ld	a,a
>+	ld	a,b
>+	ld	a,c
>+	ld	a,d
>+	ld	a,e
>+	ld	a,h
>+	ld	a,i
>+	ld	a,l
>+	ld	a,r
>+	ld	b,(hl)
>+	ld	b,(ix+9)
>+	ld	b,(iy+9)
>+	ld	b,3
>+	ld	b,a
>+	ld	b,b
>+	ld	b,c
>+	ld	b,d
>+	ld	b,e
>+	ld	b,h
>+	ld	b,l
>+	ld	bc,(0x1234)
>+	ld	bc,0x1234
>+	ld	c,(hl)
>+	ld	c,(ix+9)
>+	ld	c,(iy+9)
>+	ld	c,3
>+	ld	c,a
>+	ld	c,b
>+	ld	c,c
>+	ld	c,d
>+	ld	c,e
>+	ld	c,h
>+	ld	c,l
>+	ld	d,(hl)
>+	ld	d,(ix+9)
>+	ld	d,(iy+9)
>+	ld	d,3
>+	ld	d,a
>+	ld	d,b
>+	ld	d,c
>+	ld	d,d
>+	ld	d,e
>+	ld	d,h
>+	ld	d,l
>+	ld	de,(0x1234)
>+	ld	de,0x1234
>+	ld	e,(hl)
>+	ld	e,(ix+9)
>+	ld	e,(iy+9)
>+	ld	e,3
>+	ld	e,a
>+	ld	e,b
>+	ld	e,c
>+	ld	e,d
>+	ld	e,e
>+	ld	e,h
>+	ld	e,l
>+	ld	h,(hl)
>+	ld	h,(ix+9)
>+	ld	h,(iy+9)
>+	ld	h,3
>+	ld	h,a
>+	ld	h,b
>+	ld	h,c
>+	ld	h,d
>+	ld	h,e
>+	ld	h,h
>+	ld	h,l
>+	ld	hl,(0x1234)
>+	ld	hl,0x1234
>+	ld	i,a
>+	ld	ix,(0x1234)
>+	ld	ix,0x1234
>+	ld	iy,(0x1234)
>+	ld	iy,0x1234
>+	ld	l,(hl)
>+	ld	l,(ix+9)
>+	ld	l,(iy+9)
>+	ld	l,3
>+	ld	l,a
>+	ld	l,b
>+	ld	l,c
>+	ld	l,d
>+	ld	l,e
>+	ld	l,h
>+	ld	l,l
>+	ld	r,a
>+	ld	sp,(0x1234)
>+	ld	sp,0x1234
>+	ld	sp,hl
>+	ld	sp,ix
>+	ld	sp,iy
>+	ldd
>+	lddr
>+	ldi
>+	ldir
>+	neg
>+	nop
>+	or	(hl)
>+	or	(ix+9)
>+	or	(iy+9)
>+	or	3
>+	or	a
>+	or	b
>+	or	c
>+	or	d
>+	or	e
>+	or	h
>+	or	l
>+	otdr
>+	otir
>+	out	(c),a
>+	out	(c),b
>+	out	(c),c
>+	out	(c),d
>+	out	(c),e
>+	out	(c),h
>+	out	(c),l
>+	out	(3),a
>+	outd
>+	outi
>+	pop	af
>+	pop	bc
>+	pop	de
>+	pop	hl
>+	pop	ix
>+	pop	iy
>+	push	af
>+	push	bc
>+	push	de
>+	push	hl
>+	push	ix
>+	push	iy
>+	res	0,(hl)
>+	res	0,(ix+9)
>+	res	0,(iy+9)
>+	res	0,a
>+	res	0,b
>+	res	0,c
>+	res	0,d
>+	res	0,e
>+	res	0,h
>+	res	0,l
>+	res	1,(hl)
>+	res	1,(ix+9)
>+	res	1,(iy+9)
>+	res	1,a
>+	res	1,b
>+	res	1,c
>+	res	1,d
>+	res	1,e
>+	res	1,h
>+	res	1,l
>+	res	2,(hl)
>+	res	2,(ix+9)
>+	res	2,(iy+9)
>+	res	2,a
>+	res	2,b
>+	res	2,c
>+	res	2,d
>+	res	2,e
>+	res	2,h
>+	res	2,l
>+	res	3,(hl)
>+	res	3,(ix+9)
>+	res	3,(iy+9)
>+	res	3,a
>+	res	3,b
>+	res	3,c
>+	res	3,d
>+	res	3,e
>+	res	3,h
>+	res	3,l
>+	res	4,(hl)
>+	res	4,(ix+9)
>+	res	4,(iy+9)
>+	res	4,a
>+	res	4,b
>+	res	4,c
>+	res	4,d
>+	res	4,e
>+	res	4,h
>+	res	4,l
>+	res	5,(hl)
>+	res	5,(ix+9)
>+	res	5,(iy+9)
>+	res	5,a
>+	res	5,b
>+	res	5,c
>+	res	5,d
>+	res	5,e
>+	res	5,h
>+	res	5,l
>+	res	6,(hl)
>+	res	6,(ix+9)
>+	res	6,(iy+9)
>+	res	6,a
>+	res	6,b
>+	res	6,c
>+	res	6,d
>+	res	6,e
>+	res	6,h
>+	res	6,l
>+	res	7,(hl)
>+	res	7,(ix+9)
>+	res	7,(iy+9)
>+	res	7,a
>+	res	7,b
>+	res	7,c
>+	res	7,d
>+	res	7,e
>+	res	7,h
>+	res	7,l
>+	ret
>+	ret	c
>+	ret	m
>+	ret	nc
>+	ret	nz
>+	ret	p
>+	ret	pe
>+	ret	po
>+	ret	z
>+	reti
>+	retn
>+	rl	(hl)
>+	rl	(ix+9)
>+	rl	(iy+9)
>+	rl	a
>+	rl	b
>+	rl	c
>+	rl	d
>+	rl	e
>+	rl	h
>+	rl	l
>+	rla
>+	rlc	(hl)
>+	rlc	(ix+9)
>+	rlc	(iy+9)
>+	rlc	a
>+	rlc	b
>+	rlc	c
>+	rlc	d
>+	rlc	e
>+	rlc	h
>+	rlc	l
>+	rlca
>+	rld
>+	rr	(hl)
>+	rr	(ix+9)
>+	rr	(iy+9)
>+	rr	a
>+	rr	b
>+	rr	c
>+	rr	d
>+	rr	e
>+	rr	h
>+	rr	l
>+	rra
>+	rrc	(hl)
>+	rrc	(ix+9)
>+	rrc	(iy+9)
>+	rrc	a
>+	rrc	b
>+	rrc	c
>+	rrc	d
>+	rrc	e
>+	rrc	h
>+	rrc	l
>+	rrca
>+	rrd
>+	rst	0x00
>+	rst	0x08
>+	rst	0x10
>+	rst	0x18
>+	rst	0x20
>+	rst	0x28
>+	rst	0x30
>+	rst	0x38
>+	sbc	a,(hl)
>+	sbc	a,(ix+9)
>+	sbc	a,(iy+9)
>+	sbc	a,3
>+	sbc	a,a
>+	sbc	a,b
>+	sbc	a,c
>+	sbc	a,d
>+	sbc	a,e
>+	sbc	a,h
>+	sbc	a,l
>+	sbc	hl,bc
>+	sbc	hl,de
>+	sbc	hl,hl
>+	sbc	hl,sp
>+	scf
>+	set	0,(hl)
>+	set	0,(ix+9)
>+	set	0,(iy+9)
>+	set	0,a
>+	set	0,b
>+	set	0,c
>+	set	0,d
>+	set	0,e
>+	set	0,h
>+	set	0,l
>+	set	1,(hl)
>+	set	1,(ix+9)
>+	set	1,(iy+9)
>+	set	1,a
>+	set	1,b
>+	set	1,c
>+	set	1,d
>+	set	1,e
>+	set	1,h
>+	set	1,l
>+	set	2,(hl)
>+	set	2,(ix+9)
>+	set	2,(iy+9)
>+	set	2,a
>+	set	2,b
>+	set	2,c
>+	set	2,d
>+	set	2,e
>+	set	2,h
>+	set	2,l
>+	set	3,(hl)
>+	set	3,(ix+9)
>+	set	3,(iy+9)
>+	set	3,a
>+	set	3,b
>+	set	3,c
>+	set	3,d
>+	set	3,e
>+	set	3,h
>+	set	3,l
>+	set	4,(hl)
>+	set	4,(ix+9)
>+	set	4,(iy+9)
>+	set	4,a
>+	set	4,b
>+	set	4,c
>+	set	4,d
>+	set	4,e
>+	set	4,h
>+	set	4,l
>+	set	5,(hl)
>+	set	5,(ix+9)
>+	set	5,(iy+9)
>+	set	5,a
>+	set	5,b
>+	set	5,c
>+	set	5,d
>+	set	5,e
>+	set	5,h
>+	set	5,l
>+	set	6,(hl)
>+	set	6,(ix+9)
>+	set	6,(iy+9)
>+	set	6,a
>+	set	6,b
>+	set	6,c
>+	set	6,d
>+	set	6,e
>+	set	6,h
>+	set	6,l
>+	set	7,(hl)
>+	set	7,(ix+9)
>+	set	7,(iy+9)
>+	set	7,a
>+	set	7,b
>+	set	7,c
>+	set	7,d
>+	set	7,e
>+	set	7,h
>+	set	7,l
>+	sla	(hl)
>+	sla	(ix+9)
>+	sla	(iy+9)
>+	sla	a
>+	sla	b
>+	sla	c
>+	sla	d
>+	sla	e
>+	sla	h
>+	sla	l
>+	sra	(hl)
>+	sra	(ix+9)
>+	sra	(iy+9)
>+	sra	a
>+	sra	b
>+	sra	c
>+	sra	d
>+	sra	e
>+	sra	h
>+	sra	l
>+	srl	(hl)
>+	srl	(ix+9)
>+	srl	(iy+9)
>+	srl	a
>+	srl	b
>+	srl	c
>+	srl	d
>+	srl	e
>+	srl	h
>+	srl	l
>+	sub	(hl)
>+	sub	(ix+9)
>+	sub	(iy+9)
>+	sub	3
>+	sub	a
>+	sub	b
>+	sub	c
>+	sub	d
>+	sub	e
>+	sub	h
>+	sub	l
>+	xor	(hl)
>+	xor	(ix+9)
>+	xor	(iy+9)
>+	xor	3
>+	xor	a
>+	xor	b
>+	xor	c
>+	xor	d
>+	xor	e
>+	xor	h
>+	xor	l
>+
>+	ld	a,ixh
>+	ld	b,ixh
>+	ld	c,ixh
>+	ld	d,ixh
>+	ld	e,ixh
>+	ld	ixh,ixh
>+	ld	ixl,ixh
>+
>+	ld	a,ixl
>+	ld	b,ixl
>+	ld	c,ixl
>+	ld	d,ixl
>+	ld	e,ixl
>+	ld	ixh,ixl
>+	ld	ixl,ixl
>+
>+	ld	a,iyh
>+	ld	b,iyh
>+	ld	c,iyh
>+	ld	d,iyh
>+	ld	e,iyh
>+	ld	iyh,iyh
>+	ld	iyl,iyh
>+
>+	ld	a,iyl
>+	ld	b,iyl
>+	ld	c,iyl
>+	ld	d,iyl
>+	ld	e,iyl
>+	ld	iyh,iyl
>+	ld	iyl,iyl
>+
>+	ld	ixh,a
>+	ld	ixh,b
>+	ld	ixh,c
>+	ld	ixh,d
>+	ld	ixh,e
>+	ld	ixh,ixh
>+	ld	ixh,ixl
>+	ld	ixh,25
>+
>+	ld	ixl,a
>+	ld	ixl,b
>+	ld	ixl,c
>+	ld	ixl,d
>+	ld	ixl,e
>+	ld	ixl,ixh
>+	ld	ixl,ixl
>+	ld	ixl,25
>+
>+	ld	iyh,a
>+	ld	iyh,b
>+	ld	iyh,c
>+	ld	iyh,d
>+	ld	iyh,e
>+	ld	iyh,iyh
>+	ld	iyh,iyl
>+	ld	iyh,25
>+
>+	ld	iyl,a
>+	ld	iyl,b
>+	ld	iyl,c
>+	ld	iyl,d
>+	ld	iyl,e
>+	ld	iyl,iyh
>+	ld	iyl,iyl
>+	ld	iyl,25
>+
>+	add	a,ixh
>+	add	a,ixl
>+	add	a,iyh
>+	add	a,iyl
>+
>+	adc	a,ixh
>+	adc	a,ixl
>+	adc	a,iyh
>+	adc	a,iyl
>+
>+	cp	ixh
>+	cp	ixl
>+	cp	iyh
>+	cp	iyl
>+
>+	dec	ixh
>+	dec	ixl
>+	dec	iyh
>+	dec	iyl
>+
>+	inc	ixh
>+	inc	ixl
>+	inc	iyh
>+	inc	iyl
>+
>+	sbc	a,ixh
>+	sbc	a,ixl
>+	sbc	a,iyh
>+	sbc	a,iyl
>+
>+	sub	ixh
>+	sub	ixl
>+	sub	iyh
>+	sub	iyl
>+
>+	and	ixh
>+	and	ixl
>+	and	iyh
>+	and	iyl
>+
>+	or	ixh
>+	or	ixl
>+	or	iyh
>+	or	iyl
>+
>+	xor	ixh
>+	xor	ixl
>+	xor	iyh
>+	xor	iyl
>+
>+	in	f,(c)
>+	in	(c)
>+	out	(c),0
>+
>+	RLC	(ix+8),a
>+	RLC	(ix+8),b
>+	RLC	(ix+8),c
>+	RLC	(ix+8),d
>+	RLC	(ix+8),e
>+	RLC	(ix+8),h
>+	RLC	(ix+8),l
>+	RLC	(iy+8),a
>+	RLC	(iy+8),b
>+	RLC	(iy+8),c
>+	RLC	(iy+8),d
>+	RLC	(iy+8),e
>+	RLC	(iy+8),h
>+	RLC	(iy+8),l
>+
>+	RRC	(ix+8),a
>+	RRC	(ix+8),b
>+	RRC	(ix+8),c
>+	RRC	(ix+8),d
>+	RRC	(ix+8),e
>+	RRC	(ix+8),h
>+	RRC	(ix+8),l
>+	RRC	(iy+8),a
>+	RRC	(iy+8),b
>+	RRC	(iy+8),c
>+	RRC	(iy+8),d
>+	RRC	(iy+8),e
>+	RRC	(iy+8),h
>+	RRC	(iy+8),l
>+
>+	RL	(ix+8),a
>+	RL	(ix+8),b
>+	RL	(ix+8),c
>+	RL	(ix+8),d
>+	RL	(ix+8),e
>+	RL	(ix+8),h
>+	RL	(ix+8),l
>+	RL	(iy+8),a
>+	RL	(iy+8),b
>+	RL	(iy+8),c
>+	RL	(iy+8),d
>+	RL	(iy+8),e
>+	RL	(iy+8),h
>+	RL	(iy+8),l
>+
>+	RR	(ix+8),a
>+	RR	(ix+8),b
>+	RR	(ix+8),c
>+	RR	(ix+8),d
>+	RR	(ix+8),e
>+	RR	(ix+8),h
>+	RR	(ix+8),l
>+	RR	(iy+8),a
>+	RR	(iy+8),b
>+	RR	(iy+8),c
>+	RR	(iy+8),d
>+	RR	(iy+8),e
>+	RR	(iy+8),h
>+	RR	(iy+8),l
>+
>+	SLA	(ix+8),a
>+	SLA	(ix+8),b
>+	SLA	(ix+8),c
>+	SLA	(ix+8),d
>+	SLA	(ix+8),e
>+	SLA	(ix+8),h
>+	SLA	(ix+8),l
>+	SLA	(iy+8),a
>+	SLA	(iy+8),b
>+	SLA	(iy+8),c
>+	SLA	(iy+8),d
>+	SLA	(iy+8),e
>+	SLA	(iy+8),h
>+	SLA	(iy+8),l
>+
>+	SRA	(ix+8),a
>+	SRA	(ix+8),b
>+	SRA	(ix+8),c
>+	SRA	(ix+8),d
>+	SRA	(ix+8),e
>+	SRA	(ix+8),h
>+	SRA	(ix+8),l
>+	SRA	(iy+8),a
>+	SRA	(iy+8),b
>+	SRA	(iy+8),c
>+	SRA	(iy+8),d
>+	SRA	(iy+8),e
>+	SRA	(iy+8),h
>+	SRA	(iy+8),l
>+
>+	SLI	(ix+8),a
>+	SLI	(ix+8),b
>+	SLI	(ix+8),c
>+	SLI	(ix+8),d
>+	SLI	(ix+8),e
>+	SLI	(ix+8),h
>+	SLI	(ix+8),l
>+	SLI	(iy+8),a
>+	SLI	(iy+8),b
>+	SLI	(iy+8),c
>+	SLI	(iy+8),d
>+	SLI	(iy+8),e
>+	SLI	(iy+8),h
>+	SLI	(iy+8),l
>+
>+	SRL	(ix+8),a
>+	SRL	(ix+8),b
>+	SRL	(ix+8),c
>+	SRL	(ix+8),d
>+	SRL	(ix+8),e
>+	SRL	(ix+8),h
>+	SRL	(ix+8),l
>+	SRL	(iy+8),a
>+	SRL	(iy+8),b
>+	SRL	(iy+8),c
>+	SRL	(iy+8),d
>+	SRL	(iy+8),e
>+	SRL	(iy+8),h
>+	SRL	(iy+8),l
>+
>+	RES	0,(ix+8),a
>+	RES	0,(ix+8),b
>+	RES	0,(ix+8),c
>+	RES	0,(ix+8),d
>+	RES	0,(ix+8),e
>+	RES	0,(ix+8),h
>+	RES	0,(ix+8),l
>+	RES	0,(iy+8),a
>+	RES	0,(iy+8),b
>+	RES	0,(iy+8),c
>+	RES	0,(iy+8),d
>+	RES	0,(iy+8),e
>+	RES	0,(iy+8),h
>+	RES	0,(iy+8),l
>+	RES	1,(ix+8),a
>+	RES	1,(ix+8),b
>+	RES	1,(ix+8),c
>+	RES	1,(ix+8),d
>+	RES	1,(ix+8),e
>+	RES	1,(ix+8),h
>+	RES	1,(ix+8),l
>+	RES	1,(iy+8),a
>+	RES	1,(iy+8),b
>+	RES	1,(iy+8),c
>+	RES	1,(iy+8),d
>+	RES	1,(iy+8),e
>+	RES	1,(iy+8),h
>+	RES	1,(iy+8),l
>+	RES	2,(ix+8),a
>+	RES	2,(ix+8),b
>+	RES	2,(ix+8),c
>+	RES	2,(ix+8),d
>+	RES	2,(ix+8),e
>+	RES	2,(ix+8),h
>+	RES	2,(ix+8),l
>+	RES	2,(iy+8),a
>+	RES	2,(iy+8),b
>+	RES	2,(iy+8),c
>+	RES	2,(iy+8),d
>+	RES	2,(iy+8),e
>+	RES	2,(iy+8),h
>+	RES	2,(iy+8),l
>+	RES	3,(ix+8),a
>+	RES	3,(ix+8),b
>+	RES	3,(ix+8),c
>+	RES	3,(ix+8),d
>+	RES	3,(ix+8),e
>+	RES	3,(ix+8),h
>+	RES	3,(ix+8),l
>+	RES	3,(iy+8),a
>+	RES	3,(iy+8),b
>+	RES	3,(iy+8),c
>+	RES	3,(iy+8),d
>+	RES	3,(iy+8),e
>+	RES	3,(iy+8),h
>+	RES	3,(iy+8),l
>+	RES	4,(ix+8),a
>+	RES	4,(ix+8),b
>+	RES	4,(ix+8),c
>+	RES	4,(ix+8),d
>+	RES	4,(ix+8),e
>+	RES	4,(ix+8),h
>+	RES	4,(ix+8),l
>+	RES	4,(iy+8),a
>+	RES	4,(iy+8),b
>+	RES	4,(iy+8),c
>+	RES	4,(iy+8),d
>+	RES	4,(iy+8),e
>+	RES	4,(iy+8),h
>+	RES	4,(iy+8),l
>+	RES	5,(ix+8),a
>+	RES	5,(ix+8),b
>+	RES	5,(ix+8),c
>+	RES	5,(ix+8),d
>+	RES	5,(ix+8),e
>+	RES	5,(ix+8),h
>+	RES	5,(ix+8),l
>+	RES	5,(iy+8),a
>+	RES	5,(iy+8),b
>+	RES	5,(iy+8),c
>+	RES	5,(iy+8),d
>+	RES	5,(iy+8),e
>+	RES	5,(iy+8),h
>+	RES	5,(iy+8),l
>+	RES	6,(ix+8),a
>+	RES	6,(ix+8),b
>+	RES	6,(ix+8),c
>+	RES	6,(ix+8),d
>+	RES	6,(ix+8),e
>+	RES	6,(ix+8),h
>+	RES	6,(ix+8),l
>+	RES	6,(iy+8),a
>+	RES	6,(iy+8),b
>+	RES	6,(iy+8),c
>+	RES	6,(iy+8),d
>+	RES	6,(iy+8),e
>+	RES	6,(iy+8),h
>+	RES	6,(iy+8),l
>+	RES	7,(ix+8),a
>+	RES	7,(ix+8),b
>+	RES	7,(ix+8),c
>+	RES	7,(ix+8),d
>+	RES	7,(ix+8),e
>+	RES	7,(ix+8),h
>+	RES	7,(ix+8),l
>+	RES	7,(iy+8),a
>+	RES	7,(iy+8),b
>+	RES	7,(iy+8),c
>+	RES	7,(iy+8),d
>+	RES	7,(iy+8),e
>+	RES	7,(iy+8),h
>+	RES	7,(iy+8),l
>+
>+	SET	0,(ix+8),a
>+	SET	0,(ix+8),b
>+	SET	0,(ix+8),c
>+	SET	0,(ix+8),d
>+	SET	0,(ix+8),e
>+	SET	0,(ix+8),h
>+	SET	0,(ix+8),l
>+	SET	0,(iy+8),a
>+	SET	0,(iy+8),b
>+	SET	0,(iy+8),c
>+	SET	0,(iy+8),d
>+	SET	0,(iy+8),e
>+	SET	0,(iy+8),h
>+	SET	0,(iy+8),l
>+	SET	1,(ix+8),a
>+	SET	1,(ix+8),b
>+	SET	1,(ix+8),c
>+	SET	1,(ix+8),d
>+	SET	1,(ix+8),e
>+	SET	1,(ix+8),h
>+	SET	1,(ix+8),l
>+	SET	1,(iy+8),a
>+	SET	1,(iy+8),b
>+	SET	1,(iy+8),c
>+	SET	1,(iy+8),d
>+	SET	1,(iy+8),e
>+	SET	1,(iy+8),h
>+	SET	1,(iy+8),l
>+	SET	2,(ix+8),a
>+	SET	2,(ix+8),b
>+	SET	2,(ix+8),c
>+	SET	2,(ix+8),d
>+	SET	2,(ix+8),e
>+	SET	2,(ix+8),h
>+	SET	2,(ix+8),l
>+	SET	2,(iy+8),a
>+	SET	2,(iy+8),b
>+	SET	2,(iy+8),c
>+	SET	2,(iy+8),d
>+	SET	2,(iy+8),e
>+	SET	2,(iy+8),h
>+	SET	2,(iy+8),l
>+	SET	3,(ix+8),a
>+	SET	3,(ix+8),b
>+	SET	3,(ix+8),c
>+	SET	3,(ix+8),d
>+	SET	3,(ix+8),e
>+	SET	3,(ix+8),h
>+	SET	3,(ix+8),l
>+	SET	3,(iy+8),a
>+	SET	3,(iy+8),b
>+	SET	3,(iy+8),c
>+	SET	3,(iy+8),d
>+	SET	3,(iy+8),e
>+	SET	3,(iy+8),h
>+	SET	3,(iy+8),l
>+	SET	4,(ix+8),a
>+	SET	4,(ix+8),b
>+	SET	4,(ix+8),c
>+	SET	4,(ix+8),d
>+	SET	4,(ix+8),e
>+	SET	4,(ix+8),h
>+	SET	4,(ix+8),l
>+	SET	4,(iy+8),a
>+	SET	4,(iy+8),b
>+	SET	4,(iy+8),c
>+	SET	4,(iy+8),d
>+	SET	4,(iy+8),e
>+	SET	4,(iy+8),h
>+	SET	4,(iy+8),l
>+	SET	5,(ix+8),a
>+	SET	5,(ix+8),b
>+	SET	5,(ix+8),c
>+	SET	5,(ix+8),d
>+	SET	5,(ix+8),e
>+	SET	5,(ix+8),h
>+	SET	5,(ix+8),l
>+	SET	5,(iy+8),a
>+	SET	5,(iy+8),b
>+	SET	5,(iy+8),c
>+	SET	5,(iy+8),d
>+	SET	5,(iy+8),e
>+	SET	5,(iy+8),h
>+	SET	5,(iy+8),l
>+	SET	6,(ix+8),a
>+	SET	6,(ix+8),b
>+	SET	6,(ix+8),c
>+	SET	6,(ix+8),d
>+	SET	6,(ix+8),e
>+	SET	6,(ix+8),h
>+	SET	6,(ix+8),l
>+	SET	6,(iy+8),a
>+	SET	6,(iy+8),b
>+	SET	6,(iy+8),c
>+	SET	6,(iy+8),d
>+	SET	6,(iy+8),e
>+	SET	6,(iy+8),h
>+	SET	6,(iy+8),l
>+	SET	7,(ix+8),a
>+	SET	7,(ix+8),b
>+	SET	7,(ix+8),c
>+	SET	7,(ix+8),d
>+	SET	7,(ix+8),e
>+	SET	7,(ix+8),h
>+	SET	7,(ix+8),l
>+	SET	7,(iy+8),a
>+	SET	7,(iy+8),b
>+	SET	7,(iy+8),c
>+	SET	7,(iy+8),d
>+	SET	7,(iy+8),e
>+	SET	7,(iy+8),h
>+	SET	7,(iy+8),l
>+
>+;SLI
>+	sli	a
>+	sli	b
>+	sli	c
>+	sli	d
>+	sli	e
>+	sli	h
>+	sli	l
>+	sli	(hl)
>+	sli	(ix+7)
>+	sli	(iy-9)
>+
>+;SLL is an alias for SLI
>+	sll	a
>+	sll	b
>+	sll	c
>+	sll	d
>+	sll	e
>+	sll	h
>+	sll	l
>+	sll	(hl)
>+	sll	(ix+7)
>+	sll	(iy-9)
>+
>+;SL1 is an alias for SLI
>+	sl1	a
>+	sl1	b
>+	sl1	c
>+	sl1	d
>+	sl1	e
>+	sl1	h
>+	sl1	l
>+	sl1	(hl)
>+	sl1	(ix+7)
>+	sl1	(iy-9)
>+
>+;Z80N specific
>+	ldix
>+	ldws
>+	ldirx
>+	lddx
>+	lddrx
>+	ldpirx
>+	outinb
>+	mul	d,e
>+	add	hl,a
>+	add	de,a
>+	add	bc,a
>+	add	hl,0xbeaf
>+	add	de,0xdead
>+	add	bc,0x1234
>+	swapnib
>+	mirror
>+	push	0x1234
>+	nextreg	0x12,0x34
>+	nextreg	0x56,a
>+	pixeldn
>+	pixelad
>+	setae
>+	test	0x78
>+	bsla	de,b
>+	bsra	de,b
>+	bsrl	de,b
>+	bsrf	de,b
>+	brlc	de,b
>+	jp	(c)
>+
>+	.globl	push_value
>+	push	push_value
>+;Z80N aliases
>+	mlt	de
>+	swap	a
>+	tst	0xab
>+	.end
>diff --git a/gas/testsuite/gas/z80/z80n_reloc.d b/gas/testsuite/gas/z80/z80n_reloc.d
>new file mode 100644
>index 0000000000..8fa78e1a1d
>--- /dev/null
>+++ b/gas/testsuite/gas/z80/z80n_reloc.d
>@@ -0,0 +1,10 @@
>+#as: -z80n
>+#source: z80n_all.s
>+#objdump: -r
>+#name: Z80N big-endian relocation
>+
>+.*:[     ]+file format (coff|elf32)\-z80
>+
>+RELOCATION RECORDS FOR \[\.text\]:
>+OFFSET[   ]+TYPE[              ]+VALUE\s*
>+0*c2a[ ]+r_imm16be[           ]+push_value\s*
>diff --git a/include/coff/internal.h b/include/coff/internal.h
>index 24ac1dc75c..3336234621 100644
>--- a/include/coff/internal.h
>+++ b/include/coff/internal.h
>@@ -807,6 +807,7 @@ struct internal_reloc
> /* Z80 modes */
> #define R_OFF8    0x32		/* 8 bit signed abs, for (i[xy]+d) */
> #define R_IMM24   0x33          /* 24 bit abs */
>+#define R_IMM16BE 0x3A          /* 16 bit abs, big endian */
> /* R_JR, R_IMM8, R_IMM16, R_IMM32 - as for Z8k */
> #define R_BYTE0  0x34		/* first (lowest) 8 bits of multibyte value */
> #define R_BYTE1  0x35		/* second 8 bits of multibyte value */
>diff --git a/include/elf/z80.h b/include/elf/z80.h
>index a7f72c95bb..9b5e86fbd6 100644
>--- a/include/elf/z80.h
>+++ b/include/elf/z80.h
>@@ -30,6 +30,7 @@
> #define EF_Z80_MACH_EZ80_Z80 0x04
> #define EF_Z80_MACH_EZ80_ADL 0x84
> #define EF_Z80_MACH_GBZ80    0x05
>+#define EF_Z80_MACH_Z80N     0x06
> #define EF_Z80_MACH_MSK      0xff
> 
> /* Relocations.  */
>@@ -47,6 +48,7 @@ START_RELOC_NUMBERS (elf_z80_reloc_type)
>      RELOC_NUMBER (R_Z80_BYTE3,		10)
>      RELOC_NUMBER (R_Z80_WORD0,		11)
>      RELOC_NUMBER (R_Z80_WORD1,		12)
>+     RELOC_NUMBER (R_Z80_16_BE,		13)
> END_RELOC_NUMBERS (R_Z80_max)
> 
> #endif /* _ELF_Z80_H */
>diff --git a/ld/emultempl/z80.em b/ld/emultempl/z80.em
>index 4c36cd8465..d7dc05ea26 100644
>--- a/ld/emultempl/z80.em
>+++ b/ld/emultempl/z80.em
>@@ -36,6 +36,7 @@ fragment <<EOF
> #define M_Z180      0x40
> #define M_EZ80_Z80  0x80
> #define M_EZ80_ADL  0x100
>+#define M_Z80N      0x200
> #define M_ARCH_MASK 0xFF0
> 
> /* Bitwise or of the machine types seen so far.  */
>@@ -50,7 +51,6 @@ ${LDEMUL_BEFORE_PARSE} (void)
>   result_mach_type = 0;
> }
> 
>-
> /* Update result_mach_type.  */
> static bfd_boolean
> ${LDEMUL_RECOGNIZED_FILE} (lang_input_statement_type *entry)
>@@ -78,6 +78,9 @@ ${LDEMUL_RECOGNIZED_FILE} (lang_input_statement_type *entry)
>     case bfd_mach_z180:
>       result_mach_type |= M_Z180;
>       break;
>+    case bfd_mach_z80n:
>+      result_mach_type |= M_Z80N;
>+      break;
>     case bfd_mach_ez80_z80:
>       result_mach_type |= M_EZ80_Z80;
>       break;
>@@ -104,10 +107,12 @@ gldz80_after_open (void)
>     case M_Z80 & M_ARCH_MASK:
>     case M_R800:
>     case M_Z180:
>+    case M_Z80N:
>     case M_GBZ80:
>     case M_EZ80_Z80:
>     case M_EZ80_ADL:
>     case M_EZ80_Z80 | M_Z180:
>+    case M_EZ80_Z80 | M_Z80N:
>       /* valid combination */
>       break;
>     case M_EZ80_Z80 | M_EZ80_ADL:
>@@ -128,6 +133,8 @@ gldz80_after_open (void)
>     mach_type = bfd_mach_ez80_z80;
>   else if ((result_mach_type & M_Z180) == M_Z180)
>     mach_type = bfd_mach_z180;
>+  else if ((result_mach_type & M_Z80N) == M_Z80N)
>+    mach_type = bfd_mach_z80n;
>   else if ((result_mach_type & M_R800) == M_R800)
>     mach_type = bfd_mach_r800;
>   else if ((result_mach_type & M_GBZ80) == M_GBZ80)
>diff --git a/ld/emultempl/z80elf.em b/ld/emultempl/z80elf.em
>index 4b03e798d1..2f755c673f 100644
>--- a/ld/emultempl/z80elf.em
>+++ b/ld/emultempl/z80elf.em
>@@ -29,57 +29,112 @@ gld${EMULATION_NAME}_after_open (void);
> 
> static int result_mach_type;
> 
>+struct z80_mach_info
>+{
>+  unsigned eflags;
>+  unsigned bfd_mach;
>+  const int *compat; /* back compatible machines */
>+};
>+
>+static const int
>+back_compat_z80[] = {bfd_mach_z80, -1};
>+
>+static const int
>+back_compat_z180[] = {bfd_mach_z180, bfd_mach_z80, -1};
>+
>+static const int
>+back_compat_ez80[] = {bfd_mach_ez80_z80, bfd_mach_z180, bfd_mach_z80, -1};
>+
>+static const struct z80_mach_info
>+z80_mach_info[] =
>+{
>+  { EF_Z80_MACH_Z80,      bfd_mach_z80,       NULL },
>+  { EF_Z80_MACH_Z80,      bfd_mach_z80strict, back_compat_z80 },
>+  { EF_Z80_MACH_Z80,      bfd_mach_z80full,   back_compat_z80 },
>+  { EF_Z80_MACH_Z180,     bfd_mach_z180,      back_compat_z80 },
>+  { EF_Z80_MACH_EZ80_Z80, bfd_mach_ez80_z80,  back_compat_z180 },
>+  { EF_Z80_MACH_EZ80_ADL, bfd_mach_ez80_adl,  back_compat_ez80 },
>+  { EF_Z80_MACH_Z80N,     bfd_mach_z80n,      back_compat_z80 },
>+  { EF_Z80_MACH_GBZ80,    bfd_mach_gbz80,     NULL },
>+  { EF_Z80_MACH_R800,     bfd_mach_r800,      back_compat_z80 }
>+};
>+
>+static const struct z80_mach_info *
>+z80_mach_info_by_eflags (unsigned int eflags)
>+{
>+  const struct z80_mach_info *p;
>+  const struct z80_mach_info *e;
>+
>+  eflags &= EF_Z80_MACH_MSK;
>+  p = &z80_mach_info[0];
>+  e = &z80_mach_info[sizeof(z80_mach_info)/sizeof(*z80_mach_info)];
>+  for (; p != e; ++p)
>+    if (eflags == p->eflags)
>+      return p;
>+  return NULL;
>+}
>+
>+static const struct z80_mach_info *
>+z80_mach_info_by_mach (unsigned int bfd_mach)
>+{
>+  const struct z80_mach_info *p;
>+  const struct z80_mach_info *e;
>+
>+  p = &z80_mach_info[0];
>+  e = &z80_mach_info[sizeof(z80_mach_info)/sizeof(*z80_mach_info)];
>+  for (; p != e; ++p)
>+    if (bfd_mach == p->bfd_mach)
>+      return p;
>+  return NULL;
>+}
>+
>+static const struct z80_mach_info *
>+z80_combine_mach (const struct z80_mach_info *m1,
>+		  const struct z80_mach_info *m2)
>+{
>+  int i;
>+  int mach;
>+  if (m1->compat != NULL)
>+    for (i = 0; (mach = m1->compat[i]) >= 0; ++i)
>+      if ((unsigned)mach == m2->bfd_mach)
>+	return m1;
>+  if (m2->compat != NULL)
>+    for (i = 0; (mach = m2->compat[i]) >= 0; ++i)
>+      if ((unsigned)mach == m1->bfd_mach)
>+	return m2;
>+  /* incompatible mach */
>+  return NULL;
>+}
>+
> /* Set the machine type of the output file based on result_mach_type.  */
> static void
> z80_elf_after_open (void)
> {
>-  unsigned int mach = 0;
>+  const struct z80_mach_info *mach = NULL;
>   bfd *abfd;
> 
>   /* For now, make sure all object files are of the same architecture.
>      We may try to merge object files with different architecture together.  */
>   for (abfd = link_info.input_bfds; abfd != NULL; abfd = abfd->link.next)
>     {
>-      unsigned long new_mach;
>-      new_mach = elf_elfheader (abfd)->e_flags & 0xff;
>-      if (!mach)
>+      const struct z80_mach_info *new_mach;
>+      new_mach = z80_mach_info_by_eflags (elf_elfheader (abfd)->e_flags);
>+      if (mach == NULL)
> 	mach = new_mach;
>       else if (mach != new_mach)
>-	{
>-	  if ((new_mach == EF_Z80_MACH_R800 || mach == EF_Z80_MACH_R800) ||
>-	      (new_mach == EF_Z80_MACH_GBZ80 || mach == EF_Z80_MACH_GBZ80))
>-	    einfo (_("%F%P: %pB: Instruction set of object files mismatched\n"),
>-		   abfd);
>-	  else if (mach < new_mach)
>-	    mach = new_mach;
>-	}
>+	mach = z80_combine_mach (mach, new_mach);
>+      if (mach == NULL)
>+	einfo (_("%F%P: %pB: Instruction sets of object files incompatible\n"),
>+	       abfd);
>     }
>-  switch (mach & 0xff)
>+  if (mach != NULL)
>     {
>-    case EF_Z80_MACH_Z80:
>-      mach = bfd_mach_z80;
>-      break;
>-    case EF_Z80_MACH_Z180:
>-      mach = bfd_mach_z180;
>-      break;
>-    case EF_Z80_MACH_R800:
>-      mach = bfd_mach_r800;
>-      break;
>-    case EF_Z80_MACH_EZ80_Z80:
>-      mach = bfd_mach_ez80_z80;
>-      break;
>-    case EF_Z80_MACH_EZ80_ADL:
>-      mach = bfd_mach_ez80_adl;
>-      break;
>-    case EF_Z80_MACH_GBZ80:
>-      mach = bfd_mach_gbz80;
>-      break;
>-    default:
>-      mach = (unsigned)-1;
>+      bfd_set_arch_mach (link_info.output_bfd, bfd_arch_z80, mach->bfd_mach);
>+      result_mach_type = mach->bfd_mach;
>     }
>-
>-  bfd_set_arch_mach (link_info.output_bfd, bfd_arch_z80, mach);
>-  result_mach_type = mach;
>+  else
>+    einfo (_("%F%P: %pB: Unknown machine type\n"),
>+	   abfd);
> 
>   /* Call the standard elf routine.  */
>   gld${EMULATION_NAME}_after_open ();
>@@ -94,33 +149,13 @@ z80_elf_finish (void)
> 
>   if (bfd_get_flavour (abfd) == bfd_target_elf_flavour)
>     {
>-      unsigned e_flags;
>-      switch (result_mach_type)
>+      const struct z80_mach_info *info;
>+      info = z80_mach_info_by_mach (result_mach_type);
>+      if (info)
> 	{
>-	case bfd_mach_z80strict:
>-	case bfd_mach_z80:
>-	case bfd_mach_z80full:
>-	  e_flags = EF_Z80_MACH_Z80;
>-	  break;
>-	case bfd_mach_r800:
>-	  e_flags = EF_Z80_MACH_R800;
>-	  break;
>-	case bfd_mach_gbz80:
>-	  e_flags = EF_Z80_MACH_GBZ80;
>-	  break;
>-	case bfd_mach_z180:
>-	  e_flags = EF_Z80_MACH_Z180;
>-	  break;
>-	case bfd_mach_ez80_z80:
>-	  e_flags = EF_Z80_MACH_EZ80_Z80;
>-	  break;
>-	case bfd_mach_ez80_adl:
>-	  e_flags = EF_Z80_MACH_EZ80_ADL;
>-	  break;
>-	default:
>-	  e_flags = ~0;
>+	  elf_elfheader (abfd)->e_flags &= ~EF_Z80_MACH_MSK;
>+	  elf_elfheader (abfd)->e_flags |= info->eflags;
> 	}
>-      elf_elfheader (abfd)->e_flags = (elf_elfheader (abfd)->e_flags & ~0xff) | e_flags;
>     }
> 
>   finish_default ();
>diff --git a/ld/testsuite/ld-z80/arch_z80n.d b/ld/testsuite/ld-z80/arch_z80n.d
>new file mode 100644
>index 0000000000..69754b3d6a
>--- /dev/null
>+++ b/ld/testsuite/ld-z80/arch_z80n.d
>@@ -0,0 +1,11 @@
>+#name: Z80N arch test
>+#source: dummy1.s -z80n
>+#source: dummy2.s -z80n
>+#ld: -e 0
>+#objdump: -f
>+
>+.*:[     ]+file format (coff|elf32)\-z80
>+architecture: z80n, flags 0x[0-9a-fA-F]+:
>+.*
>+.*
>+
>diff --git a/ld/testsuite/ld-z80/comb_arch_z80_z80n.d b/ld/testsuite/ld-z80/comb_arch_z80_z80n.d
>new file mode 100644
>index 0000000000..96319a2a8b
>--- /dev/null
>+++ b/ld/testsuite/ld-z80/comb_arch_z80_z80n.d
>@@ -0,0 +1,11 @@
>+#name: Z80/Z80N arch combination test
>+#source: dummy1.s -z80
>+#source: dummy2.s -z80n
>+#ld: -e 0
>+#objdump: -f
>+
>+.*:[     ]+file format (coff|elf32)\-z80
>+architecture: z80n, flags 0x[0-9a-fA-F]+:
>+.*
>+.*
>+
>diff --git a/ld/testsuite/ld-z80/labels.s b/ld/testsuite/ld-z80/labels.s
>index a957fef782..395cfb2e6f 100644
>--- a/ld/testsuite/ld-z80/labels.s
>+++ b/ld/testsuite/ld-z80/labels.s
>@@ -9,6 +9,9 @@
> 	.globl	label8
> 	.globl	label9
> 	.globl	value8
>+	.globl	value8_1
>+	.globl	value8_2
>+	.globl	value8_3
> 	.globl	value16
> 	.globl	value24
> 	.globl	value32
>@@ -35,6 +38,9 @@ label9:
> 	cpl
> 
> value8	.equ 0x12
>+value8_1	.equ 0xab
>+value8_2	.equ 0xcd
>+value8_3	.equ 0xef
> value16	.equ	0x1234
> value24	.equ	0x123456
> value32	.equ	0x12345678
>diff --git a/ld/testsuite/ld-z80/relocs.s b/ld/testsuite/ld-z80/relocs.s
>index 131a702158..422b067c4a 100644
>--- a/ld/testsuite/ld-z80/relocs.s
>+++ b/ld/testsuite/ld-z80/relocs.s
>@@ -12,6 +12,9 @@
> 	.globl	label9
> 
> 	.globl	value8
>+	.globl	value8_1
>+	.globl	value8_2
>+	.globl	value8_3
> 	.globl	value16
> 	.globl	value24
> 	.globl	value32
>@@ -74,6 +77,14 @@ field_0_1	.equ	field_0+90
> 	ld	h,(value32 + 0x12345678) >> 8
> 	ld	l,(value32 + 0x12345678) >> 0
> 
>+	.ifdef Z80N
>+	push	label1
>+	push	value16
>+	nextreg	value8_1,value8_2
>+	nextreg	value8_3,a
>+	ld	a,a
>+	.endif
>+
> 	.data
> 	.db	value8
> 	.dw	value16
>diff --git a/ld/testsuite/ld-z80/relocs_f_z80n.d b/ld/testsuite/ld-z80/relocs_f_z80n.d
>new file mode 100644
>index 0000000000..8cf0ab8844
>--- /dev/null
>+++ b/ld/testsuite/ld-z80/relocs_f_z80n.d
>@@ -0,0 +1,86 @@
>+#name: Z80N forward relocation
>+#as: -z80n --defsym Z80N=1
>+#source: relocs.s
>+#source: labels.s
>+#ld: -e 0 -Ttext 0x100 -Tdata 0x200
>+#objdump: -d
>+
>+
>+.*:[     ]+file format (coff|elf32)\-z80
>+
>+
>+.* \.text:
>+
>+0+100 <.*>:
>+[ ]+100:[ 	]+cd 7d 01[    	]+call 0x017d
>+[ ]+103:[ 	]+c4 7e 01[    	]+call nz,0x017e
>+[ ]+106:[ 	]+cc 7f 01[    	]+call z,0x017f
>+[ ]+109:[ 	]+d4 80 01[    	]+call nc,0x0180
>+[ ]+10c:[ 	]+dc 81 01[    	]+call c,0x0181
>+[ ]+10f:[ 	]+e4 82 01[    	]+call po,0x0182
>+[ ]+112:[ 	]+ec 83 01[    	]+call pe,0x0183
>+[ ]+115:[ 	]+f4 84 01[    	]+call p,0x0184
>+[ ]+118:[ 	]+fc 85 01[    	]+call m,0x0185
>+[ ]+11b:[ 	]+c3 7d 01[    	]+jp 0x017d
>+[ ]+11e:[ 	]+c2 7e 01[    	]+jp nz,0x017e
>+[ ]+121:[ 	]+ca 7f 01[    	]+jp z,0x017f
>+[ ]+124:[ 	]+d2 80 01[    	]+jp nc,0x0180
>+[ ]+127:[ 	]+da 81 01[    	]+jp c,0x0181
>+[ ]+12a:[ 	]+e2 82 01[    	]+jp po,0x0182
>+[ ]+12d:[ 	]+ea 83 01[    	]+jp pe,0x0183
>+[ ]+130:[ 	]+f2 84 01[    	]+jp p,0x0184
>+[ ]+133:[ 	]+fa 85 01[    	]+jp m,0x0185
>+[ ]+136:[ 	]+dd 6e 05[    	]+ld l,$ix\+5$
>+[ ]+139:[ 	]+dd 7e 03[    	]+ld a,$ix\+3$
>+[ ]+13c:[ 	]+dd 4e fa[    	]+ld c,$ix\-6$
>+[ ]+13f:[ 	]+dd 46 f9[    	]+ld b,$ix\-7$
>+[ ]+142:[ 	]+fd 75 fb[    	]+ld $iy\-5$,l
>+[ ]+145:[ 	]+fd 77 03[    	]+ld $iy\+3$,a
>+[ ]+148:[ 	]+fd 71 0e[    	]+ld $iy\+14$,c
>+[ ]+14b:[ 	]+fd 70 0f[    	]+ld $iy\+15$,b
>+[ ]+14e:[ 	]+fd 66 5d[    	]+ld h,$iy\+93$
>+[ ]+151:[ 	]+11 34 12[    	]+ld de,0x1234
>+[ ]+154:[ 	]+21 78 56[    	]+ld hl,0x5678
>+[ ]+157:[ 	]+11 68 24[    	]+ld de,0x2468
>+[ ]+15a:[ 	]+21 f0 ac[    	]+ld hl,0xacf0
>+[ ]+15d:[ 	]+16 12[       	]+ld d,0x12
>+[ ]+15f:[ 	]+1e 34[       	]+ld e,0x34
>+[ ]+161:[ 	]+26 56[       	]+ld h,0x56
>+[ ]+163:[ 	]+2e 78[       	]+ld l,0x78
>+[ ]+165:[ 	]+16 24[       	]+ld d,0x24
>+[ ]+167:[ 	]+1e 68[       	]+ld e,0x68
>+[ ]+169:[ 	]+26 ac[       	]+ld h,0xac
>+[ ]+16b:[ 	]+2e f0[       	]+ld l,0xf0
>+[ ]+16d:[ 	]+ed 8a 01 7d[ 	]+push 0x017d
>+[ ]+171:[ 	]+ed 8a 12 34[ 	]+push 0x1234
>+[ ]+175:[ 	]+ed 91 ab cd[ 	]+nextreg 0xab,0xcd
>+[ ]+179:[ 	]+ed 92 ef[    	]+nextreg 0xef,a
>+[ ]+17c:[ 	]+7f[          	]+ld a,a
>+
>+0+17d <label1>:
>+[ ]+17d:[ 	]+78[          	]+ld a,b
>+
>+0+17e <label2>:
>+[ ]+17e:[ 	]+79[          	]+ld a,c
>+
>+0+17f <label3>:
>+[ ]+17f:[ 	]+7a[          	]+ld a,d
>+
>+0+180 <label4>:
>+[ ]+180:[ 	]+7b[          	]+ld a,e
>+
>+0+181 <label5>:
>+[ ]+181:[ 	]+7c[          	]+ld a,h
>+
>+0+182 <label6>:
>+[ ]+182:[ 	]+7d[          	]+ld a,l
>+
>+0+183 <label7>:
>+[ ]+183:[ 	]+7e[          	]+ld a,$hl$
>+
>+0+184 <label8>:
>+[ ]+184:[ 	]+7f[          	]+ld a,a
>+
>+0+185 <label9>:
>+[ ]+185:[ 	]+2f[          	]+cpl
>+#pass
>diff --git a/opcodes/z80-dis.c b/opcodes/z80-dis.c
>index 9d7f14ab3a..724cdd9fe5 100644
>--- a/opcodes/z80-dis.c
>+++ b/opcodes/z80-dis.c
>@@ -52,6 +52,7 @@ struct tab_elt
> #define INSS_EZ80_Z80 (1 << bfd_mach_ez80_z80)
> #define INSS_EZ80_ADL (1 << bfd_mach_ez80_adl)
> #define INSS_EZ80 (INSS_EZ80_ADL | INSS_EZ80_Z80)
>+#define INSS_Z80N (1 << bfd_mach_z80n)
> 
> #define TXTSIZ 24
> /* Names of 16-bit registers.  */
>@@ -195,6 +196,27 @@ prt_n (struct buffer *buf, disassemble_info * info, const char *txt)
>   return buf->n_used;
> }
> 
>+static int
>+prt_n_n (struct buffer *buf, disassemble_info * info, const char *txt)
>+{
>+  char mytxt[TXTSIZ];
>+  int n;
>+  unsigned char *p;
>+
>+  p = (unsigned char*) buf->data + buf->n_fetch;
>+
>+  if (fetch_data (buf, info, 1))
>+    {
>+      n = p[0];
>+      snprintf (mytxt, TXTSIZ, txt, n);
>+      buf->n_used = buf->n_fetch;
>+    }
>+  else
>+    buf->n_used = -1;
>+
>+  return prt_n (buf, info, mytxt);
>+}
>+
> static int
> prt_r_n (struct buffer *buf, disassemble_info * info, const char *txt)
> {
>@@ -412,7 +434,9 @@ dump (struct buffer *buf, disassemble_info * info, const char *txt)
> /* Table to disassemble machine codes with prefix 0xED.  */
> struct tab_elt opc_ed[] =
> {
>-  { 0x30, 0xFE, dump, "xx", INSS_ALL },
>+  { 0x30, 0xFF, prt, "mul d,e", INSS_Z80N },
>+  { 0x31, 0xFF, prt, "add hl,a", INSS_Z80N },
>+  { 0x30, 0xFE, dump, "xx", INSS_ALL }, /* do not move this line */
>   { 0x00, 0xC7, prt_r_n, "in0 %s,(0x%%02x)", INSS_Z180|INSS_EZ80 },
>   { 0x01, 0xC7, prt_r_n, "out0 (0x%%02x),%s", INSS_Z180|INSS_EZ80 },
>   { 0x32, 0xFF, prt_d, "lea ix,ix%+d", INSS_EZ80 },
>@@ -424,17 +448,30 @@ struct tab_elt opc_ed[] =
>   { 0x07, 0xFF, prt, "ld bc,(hl)", INSS_EZ80 },
>   { 0x0F, 0xCF, prt_rr, "ld (hl),", INSS_EZ80 },
>   { 0x17, 0xFF, prt, "ld de,(hl)", INSS_EZ80 },
>+  { 0x23, 0xFF, prt, "swapnib", INSS_Z80N },
>+  { 0x24, 0xFF, prt, "mirror", INSS_Z80N },
>   { 0x27, 0xFF, prt, "ld hl,(hl)", INSS_EZ80 },
>+  { 0x27, 0xFF, prt_n, "test 0x%02x", INSS_Z80N },
>+  { 0x28, 0xFF, prt, "bsla de,b", INSS_Z80N },
>+  { 0x29, 0xFF, prt, "bsra de,b", INSS_Z80N },
>+  { 0x2A, 0xFF, prt, "bsrl de,b", INSS_Z80N },
>+  { 0x2B, 0xFF, prt, "bsrf de,b", INSS_Z80N },
>+  { 0x2C, 0xFF, prt, "bslc de,b", INSS_Z80N },
>+  { 0x32, 0xFF, prt, "add de,a", INSS_Z80N },
>+  { 0x33, 0xFF, prt, "add bc,a", INSS_Z80N },
>+  { 0x34, 0xFF, prt_nn, "add hl,0x%04x", INSS_Z80N },
>+  { 0x35, 0xFF, prt_nn, "add de,0x%04x", INSS_Z80N },
>+  { 0x36, 0xFF, prt_nn, "add bc,0x%04x", INSS_Z80N },
>   { 0x36, 0xFF, prt, "ld iy,(hl)", INSS_EZ80 },
>   { 0x37, 0xFF, prt, "ld ix,(hl)", INSS_EZ80 },
>   { 0x3E, 0xFF, prt, "ld (hl),iy", INSS_EZ80 },
>   { 0x3F, 0xFF, prt, "ld (hl),ix", INSS_EZ80 },
>-  { 0x70, 0xFF, prt, "in f,(c)", INSS_Z80 | INSS_R800 },
>+  { 0x70, 0xFF, prt, "in f,(c)", INSS_Z80 | INSS_R800 | INSS_Z80N },
>   { 0x70, 0xFF, dump, "xx", INSS_ALL },
>   { 0x40, 0xC7, prt_r, "in %s,(bc)", INSS_EZ80 },
>   { 0x40, 0xC7, prt_r, "in %s,(c)", INSS_ALL },
>-  { 0x71, 0xFF, prt, "out (c),0", INSS_Z80 },
>-  { 0x70, 0xFF, dump, "xx", INSS_ALL },
>+  { 0x71, 0xFF, prt, "out (c),0", INSS_Z80 | INSS_Z80N },
>+  { 0x71, 0xFF, dump, "xx", INSS_ALL },
>   { 0x41, 0xC7, prt_r, "out (bc),%s", INSS_EZ80 },
>   { 0x41, 0xC7, prt_r, "out (c),%s", INSS_ALL },
>   { 0x42, 0xCF, prt_rr, "sbc hl,", INSS_ALL },
>@@ -459,24 +496,38 @@ struct tab_elt opc_ed[] =
>   { 0x65, 0xFF, prt_d, "pea ix%+d", INSS_EZ80 },
>   { 0x66, 0xFF, prt_d, "pea iy%+d", INSS_EZ80 },
>   { 0x67, 0xFF, prt, "rrd", INSS_ALL },
>+  { 0x6D, 0xFF, prt, "ld mb,a", INSS_EZ80 },
>+  { 0x6E, 0xFF, prt, "ld a,mb", INSS_EZ80 },
>   { 0x6F, 0xFF, prt, "rld", INSS_ALL },
>   { 0x74, 0xFF, prt_n, "tstio 0x%02x", INSS_Z180|INSS_EZ80 },
>   { 0x76, 0xFF, prt, "slp", INSS_Z180|INSS_EZ80 },
>+  { 0x7D, 0xFF, prt, "stmix", INSS_EZ80 },
>+  { 0x7E, 0xFF, prt, "rsmix", INSS_EZ80 },
>   { 0x82, 0xE6, cism, "", INSS_Z180|INSS_EZ80 },
>   { 0x84, 0xC7, cis2, "", INSS_EZ80 },
>+  { 0x8A, 0xFF, prt_n_n, "push 0x%02x%%02x", INSS_Z80N },
>+  { 0x90, 0xFF, prt, "outinb", INSS_Z80N },
>+  { 0x91, 0xFF, prt_n_n, "nextreg 0x%02x,0x%%02x", INSS_Z80N },
>+  { 0x92, 0xFF, prt_n, "nextreg 0x%02x,a", INSS_Z80N },
>+  { 0x93, 0xFF, prt, "pixeldn", INSS_Z80N },
>+  { 0x94, 0xFF, prt, "pixelad", INSS_Z80N },
>+  { 0x95, 0xFF, prt, "setae", INSS_Z80N },
>+  { 0x98, 0xFF, prt, "jp (c)", INSS_Z80N },
>   { 0xA0, 0xE4, cis, "", INSS_ALL },
>-  { 0x7D, 0xFF, prt, "stmix", INSS_EZ80 },
>-  { 0x7E, 0xFF, prt, "rsmix", INSS_EZ80 },
>-  { 0x6D, 0xFF, prt, "ld mb,a", INSS_EZ80 },
>-  { 0x6E, 0xFF, prt, "ld a,mb", INSS_EZ80 },
>-  { 0xC7, 0xFF, prt, "ld i,hl", INSS_EZ80 },
>-  { 0xD7, 0xFF, prt, "ld hl,i", INSS_EZ80 },
>+  { 0xA4, 0xFF, prt, "ldix", INSS_Z80N },
>+  { 0xAC, 0xFF, prt, "lddx", INSS_Z80N },
>+  { 0xA5, 0xFF, prt, "ldws", INSS_Z80N },
>+  { 0xB4, 0xFF, prt, "ldirx", INSS_Z80N },
>+  { 0xB7, 0xFF, prt, "ldpirx", INSS_Z80N },
>+  { 0xBC, 0xFF, prt, "lddrx", INSS_Z80N },
>   { 0xC2, 0xFF, prt, "inirx", INSS_EZ80 },
>   { 0xC3, 0xFF, prt, "otirx", INSS_EZ80 },
>+  { 0xC7, 0xFF, prt, "ld i,hl", INSS_EZ80 },
>   { 0xCA, 0xFF, prt, "indrx", INSS_EZ80 },
>   { 0xCB, 0xFF, prt, "otdrx", INSS_EZ80 },
>   { 0xC3, 0xFF, prt, "muluw hl,bc", INSS_R800 },
>   { 0xC5, 0xE7, prt_r, "mulub a,%s", INSS_R800 },
>+  { 0xD7, 0xFF, prt, "ld hl,i", INSS_EZ80 },
>   { 0xF3, 0xFF, prt, "muluw hl,sp", INSS_R800 },
>   { 0x00, 0x00, dump, "xx", INSS_ALL }
> };
>-- 
>2.17.1
>
>
>From fa2ebc87eb9d03494b8a5527cd6c16f86e2372ba Mon Sep 17 00:00:00 2001
>From: Sergey Belyashov <Sergey.Belyashov@gmail.com>
>Date: Fri, 31 Jan 2020 18:23:24 +0300
>Subject: [PATCH 4/7] [Z80] Fix LD test failures for COFF target
>
>---
> bfd/elf32-z80.c           | 105 ++++++++++++++----
> ld/emulparams/elf32z80.sh |   2 +-
> ld/emultempl/z80.em       | 224 +++++++++++++++++++-------------------
> ld/emultempl/z80elf.em    | 168 ----------------------------
> 4 files changed, 195 insertions(+), 304 deletions(-)
> delete mode 100644 ld/emultempl/z80elf.em
>
>diff --git a/bfd/elf32-z80.c b/bfd/elf32-z80.c
>index 0574c703d8..743cc7e5af 100644
>--- a/bfd/elf32-z80.c
>+++ b/bfd/elf32-z80.c
>@@ -344,42 +344,99 @@ z80_info_to_howto_rel (bfd *abfd, arelent *cache_ptr, Elf_Internal_Rela *dst)
>   return FALSE;
> }
> 
>+/* The final processing done just before writing out a Z80 ELF object
>+   file.  This gets the Z80 architecture right based on the machine
>+   number.  */
>+
> static bfd_boolean
>-z80_elf_set_mach_from_flags (bfd *abfd)
>+z80_elf_final_write_processing (bfd *abfd)
> {
>-  int mach;
>-  switch (elf_elfheader (abfd)->e_flags)
>+  unsigned long val = bfd_get_mach (abfd);
>+
>+  switch (val)
>     {
>-    case EF_Z80_MACH_GBZ80:
>-      mach = bfd_mach_gbz80;
>+    default:
>+      _bfd_error_handler (_("%pB: unsupported bfd mach %#lx"),
>+			  abfd, val);
>+      /* fall through */
>+    case bfd_mach_z80:
>+    case bfd_mach_z80full:
>+    case bfd_mach_z80strict:
>+      val = EF_Z80_MACH_Z80;
>       break;
>-    case EF_Z80_MACH_Z80:
>-      mach = bfd_mach_z80;
>+    case bfd_mach_gbz80:
>+      val = EF_Z80_MACH_GBZ80;
>       break;
>-    case EF_Z80_MACH_Z180:
>-      mach = bfd_mach_z180;
>+    case bfd_mach_z80n:
>+      val = EF_Z80_MACH_Z80N;
>       break;
>-    case EF_Z80_MACH_EZ80_Z80:
>-      mach = bfd_mach_ez80_z80;
>+    case bfd_mach_z180:
>+      val = EF_Z80_MACH_Z180;
>       break;
>-    case EF_Z80_MACH_EZ80_ADL:
>-      mach = bfd_mach_ez80_adl;
>+    case bfd_mach_ez80_z80:
>+      val = EF_Z80_MACH_EZ80_Z80;
>       break;
>-    case EF_Z80_MACH_R800:
>-      mach = bfd_mach_r800;
>+    case bfd_mach_ez80_adl:
>+      val = EF_Z80_MACH_EZ80_ADL;
>       break;
>-    case EF_Z80_MACH_Z80N:
>-      mach = bfd_mach_z80n;
>-      break;
>-    default:
>-      mach = bfd_mach_z80;
>+    case bfd_mach_r800:
>+      val = EF_Z80_MACH_R800;
>       break;
>     }
>+  elf_elfheader (abfd)->e_machine = EM_Z80;
>+  elf_elfheader (abfd)->e_flags &= ~EF_Z80_MACH_MSK;
>+  elf_elfheader (abfd)->e_flags |= val;
>+  return _bfd_elf_final_write_processing (abfd);
>+}
>+
>+/* Set the right machine number.  */
>+static bfd_boolean
>+z80_elf_object_p (bfd *abfd)
>+{
>+  unsigned int mach;
> 
>-  bfd_default_set_arch_mach (abfd, bfd_arch_z80, mach);
>-  return TRUE;
>+  if (elf_elfheader (abfd)->e_machine == EM_Z80)
>+    {
>+      int e_mach = elf_elfheader (abfd)->e_flags & EF_Z80_MACH_MSK;
>+      switch (e_mach)
>+        {
>+        default:
>+	  _bfd_error_handler (_("%pB: unsupported mach %#x"),
>+			      abfd, e_mach);
>+	  /* fall through */
>+	case EF_Z80_MACH_Z80:
>+	  mach = bfd_mach_z80;
>+	  break;
>+	case EF_Z80_MACH_GBZ80:
>+	  mach = bfd_mach_gbz80;
>+	  break;
>+	case EF_Z80_MACH_Z180:
>+	  mach = bfd_mach_z180;
>+	  break;
>+	case EF_Z80_MACH_EZ80_Z80:
>+	  mach = bfd_mach_ez80_z80;
>+	  break;
>+	case EF_Z80_MACH_EZ80_ADL:
>+	  mach = bfd_mach_ez80_adl;
>+	  break;
>+	case EF_Z80_MACH_R800:
>+	  mach = bfd_mach_r800;
>+	  break;
>+	case EF_Z80_MACH_Z80N:
>+	  mach = bfd_mach_z80n;
>+	  break;
>+        }
>+    }
>+  else
>+    {
>+      _bfd_error_handler (_("%pB: unsupported arch %#x"),
>+			  abfd, elf_elfheader (abfd)->e_machine);
>+      mach = bfd_mach_z80;
>+    }
>+  return bfd_default_set_arch_mach (abfd, bfd_arch_z80, mach);
> }
> 
>+
> static int
> z80_is_local_label_name (bfd *        abfd ATTRIBUTE_UNUSED,
>                          const char * name)
>@@ -450,7 +507,9 @@ z80_elf_16_be_reloc (bfd *abfd,
> 
> #define elf_info_to_howto			NULL
> #define elf_info_to_howto_rel			z80_info_to_howto_rel
>-#define elf_backend_object_p			z80_elf_set_mach_from_flags
>+#define elf_backend_final_write_processing	z80_elf_final_write_processing
>+#define elf_backend_object_p			z80_elf_object_p
> #define bfd_elf32_bfd_is_local_label_name	z80_is_local_label_name
> 
>+
> #include "elf32-target.h"
>diff --git a/ld/emulparams/elf32z80.sh b/ld/emulparams/elf32z80.sh
>index c4aa444694..45a1112103 100644
>--- a/ld/emulparams/elf32z80.sh
>+++ b/ld/emulparams/elf32z80.sh
>@@ -11,7 +11,7 @@ TEXT_START_ADDR=0x100
> #TEXT_LENGTH=0
> #DATA_ORIGIN=0
> #DATA_LENGTH=0
>-EXTRA_EM_FILE=z80elf
>+EXTRA_EM_FILE=z80
> 
> #FUSE_NAME=fuse
> 
>diff --git a/ld/emultempl/z80.em b/ld/emultempl/z80.em
>index d7dc05ea26..81385e7433 100644
>--- a/ld/emultempl/z80.em
>+++ b/ld/emultempl/z80.em
>@@ -19,136 +19,136 @@
> # Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
> # MA 02110-1301, USA.
> 
>-LDEMUL_BEFORE_PARSE=gldz80_before_parse
>-LDEMUL_RECOGNIZED_FILE=gldz80_recognized_file
>-LDEMUL_AFTER_OPEN=gldz80_after_open
>-
> fragment <<EOF
> /* --- \begin{z80.em} */
>-/* Codes for machine types, bitwise or gives the code to use for the
>-   output.  */
>-#define M_Z80STRICT 0x01
>-#define M_Z80       0x03
>-#define M_Z80FULL   0x07
>-#define M_R800      0x10
>-#define M_Z80ANY    0x0f
>-#define M_GBZ80     0x20
>-#define M_Z180      0x40
>-#define M_EZ80_Z80  0x80
>-#define M_EZ80_ADL  0x100
>-#define M_Z80N      0x200
>-#define M_ARCH_MASK 0xFF0
>-
>-/* Bitwise or of the machine types seen so far.  */
>-static int result_mach_type;
>+
>+#include "elf/z80.h"
> 
> static void
>-${LDEMUL_BEFORE_PARSE} (void)
>+gld${EMULATION_NAME}_after_open (void);
>+
>+static int result_mach_type;
>+
>+struct z80_mach_info
> {
>-#ifndef TARGET_			/* I.e., if not generic.  */
>-  ldfile_set_output_arch ("`echo ${ARCH}`", bfd_arch_unknown);
>-#endif /* not TARGET_ */
>-  result_mach_type = 0;
>-}
>+  unsigned eflags;
>+  unsigned bfd_mach;
>+  const int *compat; /* back compatible machines */
>+};
>+
>+static const int
>+back_compat_z80[] = {bfd_mach_z80, -1};
> 
>-/* Update result_mach_type.  */
>-static bfd_boolean
>-${LDEMUL_RECOGNIZED_FILE} (lang_input_statement_type *entry)
>+static const int
>+back_compat_z180[] = {bfd_mach_z180, bfd_mach_z80, -1};
>+
>+static const int
>+back_compat_ez80[] = {bfd_mach_ez80_z80, bfd_mach_z180, bfd_mach_z80, -1};
>+
>+static const struct z80_mach_info
>+z80_mach_info[] =
> {
>-  unsigned long mach_type;
>+  { EF_Z80_MACH_Z80,      bfd_mach_z80,       NULL },
>+  { EF_Z80_MACH_Z80,      bfd_mach_z80strict, back_compat_z80 },
>+  { EF_Z80_MACH_Z80,      bfd_mach_z80full,   back_compat_z80 },
>+  { EF_Z80_MACH_Z180,     bfd_mach_z180,      back_compat_z80 },
>+  { EF_Z80_MACH_EZ80_Z80, bfd_mach_ez80_z80,  back_compat_z180 },
>+  { EF_Z80_MACH_EZ80_ADL, bfd_mach_ez80_adl,  back_compat_ez80 },
>+  { EF_Z80_MACH_Z80N,     bfd_mach_z80n,      back_compat_z80 },
>+  { EF_Z80_MACH_GBZ80,    bfd_mach_gbz80,     NULL },
>+  { EF_Z80_MACH_R800,     bfd_mach_r800,      back_compat_z80 }
>+};
>+/*
>+static const struct z80_mach_info *
>+z80_mach_info_by_eflags (unsigned int eflags)
>+{
>+  const struct z80_mach_info *p;
>+  const struct z80_mach_info *e;
> 
>-  mach_type = bfd_get_mach (entry->the_bfd);
>-  switch (mach_type)
>-    {
>-    case bfd_mach_z80strict:
>-      result_mach_type |= M_Z80STRICT;
>-      break;
>-    case bfd_mach_z80:
>-      result_mach_type |= M_Z80;
>-      break;
>-    case bfd_mach_z80full:
>-      result_mach_type |= M_Z80FULL;
>-      break;
>-    case bfd_mach_r800:
>-      result_mach_type |= M_R800;
>-      break;
>-    case bfd_mach_gbz80:
>-      result_mach_type |= M_GBZ80;
>-      break;
>-    case bfd_mach_z180:
>-      result_mach_type |= M_Z180;
>-      break;
>-    case bfd_mach_z80n:
>-      result_mach_type |= M_Z80N;
>-      break;
>-    case bfd_mach_ez80_z80:
>-      result_mach_type |= M_EZ80_Z80;
>-      break;
>-    case bfd_mach_ez80_adl:
>-      result_mach_type |= M_EZ80_ADL;
>-      break;
>-    default:
>-      einfo (_("%P: warning: unknown machine type %u"), (unsigned)mach_type);
>-      result_mach_type |= M_Z80ANY;
>-    }
>-  return FALSE;
>+  eflags &= EF_Z80_MACH_MSK;
>+  p = &z80_mach_info[0];
>+  e = &z80_mach_info[sizeof(z80_mach_info)/sizeof(*z80_mach_info)];
>+  for (; p != e; ++p)
>+    if (eflags == p->eflags)
>+      return p;
>+  return NULL;
>+}*/
>+
>+static const struct z80_mach_info *
>+z80_mach_info_by_mach (unsigned int bfd_mach)
>+{
>+  const struct z80_mach_info *p;
>+  const struct z80_mach_info *e;
>+
>+  p = &z80_mach_info[0];
>+  e = &z80_mach_info[sizeof(z80_mach_info)/sizeof(*z80_mach_info)];
>+  for (; p != e; ++p)
>+    if (bfd_mach == p->bfd_mach)
>+      return p;
>+  return NULL;
>+}
>+
>+static const struct z80_mach_info *
>+z80_combine_mach (const struct z80_mach_info *m1,
>+		  const struct z80_mach_info *m2)
>+{
>+  int i;
>+  int mach;
>+  if (m1->compat != NULL)
>+    for (i = 0; (mach = m1->compat[i]) >= 0; ++i)
>+      if ((unsigned)mach == m2->bfd_mach)
>+	return m1;
>+  if (m2->compat != NULL)
>+    for (i = 0; (mach = m2->compat[i]) >= 0; ++i)
>+      if ((unsigned)mach == m1->bfd_mach)
>+	return m2;
>+  /* incompatible mach */
>+  return NULL;
> }
> 
> /* Set the machine type of the output file based on result_mach_type.  */
> static void
>-gldz80_after_open (void)
>+z80_after_open (void)
> {
>-  unsigned long mach_type;
>+  const struct z80_mach_info *mach = NULL;
>+  bfd *abfd;
> 
>-  after_open_default ();
>-
>-  switch (result_mach_type & M_ARCH_MASK)
>+  /* For now, make sure all object files are of the same architecture.
>+     We may try to merge object files with different architecture together.  */
>+  for (abfd = link_info.input_bfds; abfd != NULL; abfd = abfd->link.next)
>     {
>-    case M_Z80 & M_ARCH_MASK:
>-    case M_R800:
>-    case M_Z180:
>-    case M_Z80N:
>-    case M_GBZ80:
>-    case M_EZ80_Z80:
>-    case M_EZ80_ADL:
>-    case M_EZ80_Z80 | M_Z180:
>-    case M_EZ80_Z80 | M_Z80N:
>-      /* valid combination */
>-      break;
>-    case M_EZ80_Z80 | M_EZ80_ADL:
>-    case M_EZ80_Z80 | M_EZ80_ADL | M_Z180:
>-    case M_EZ80_ADL | M_Z180:
>-      /* combination may cause invalid objdump output */
>-      /* but it is possible for mixed ADL/Z80 code */
>-      einfo (_("%P: warning: mixing ADL and Z80 mode binaries, objdump may generate invalid output"));
>-      break;
>-    default:
>-      /* invalid combination: for example Z180 + R800 */
>-      einfo (_("%P: warning: incompatible object files linked, result code might not work"));
>+      const struct z80_mach_info *new_mach;
>+      /*new_mach = z80_mach_info_by_eflags (elf_elfheader (abfd)->e_flags);*/
>+      new_mach = z80_mach_info_by_mach(bfd_get_mach (abfd));
>+      if (mach == NULL)
>+	mach = new_mach;
>+      else if (mach != new_mach)
>+	mach = z80_combine_mach (mach, new_mach);
>+      if (mach == NULL)
>+	einfo (_("%F%P: %pB: Instruction sets of object files incompatible\n"),
>+	       abfd);
>+    }
>+  if (mach != NULL)
>+    {
>+      bfd_set_arch_mach (link_info.output_bfd, bfd_arch_z80, mach->bfd_mach);
>+      result_mach_type = mach->bfd_mach;
>     }
>-
>-  if ((result_mach_type & M_EZ80_ADL) == M_EZ80_ADL)
>-    mach_type = bfd_mach_ez80_adl;
>-  else if ((result_mach_type & M_EZ80_Z80) == M_EZ80_Z80)
>-    mach_type = bfd_mach_ez80_z80;
>-  else if ((result_mach_type & M_Z180) == M_Z180)
>-    mach_type = bfd_mach_z180;
>-  else if ((result_mach_type & M_Z80N) == M_Z80N)
>-    mach_type = bfd_mach_z80n;
>-  else if ((result_mach_type & M_R800) == M_R800)
>-    mach_type = bfd_mach_r800;
>-  else if ((result_mach_type & M_GBZ80) == M_GBZ80)
>-    mach_type = bfd_mach_gbz80;
>-  else if ((result_mach_type & M_Z80FULL) == M_Z80FULL)
>-    mach_type = bfd_mach_z80full; /* TODO: remove it */
>-  else if ((result_mach_type & M_Z80) == M_Z80)
>-    mach_type = bfd_mach_z80;
>-  else if ((result_mach_type & M_Z80STRICT) == M_Z80STRICT)
>-    mach_type = bfd_mach_z80strict; /* TODO: remove this */
>   else
>-    mach_type = bfd_arch_unknown;
>+    einfo (_("%F%P: %pB: Unknown machine type\n"),
>+	   abfd);
> 
>-  bfd_set_arch_mach (link_info.output_bfd, bfd_arch_z80, mach_type);
>+  /* Call the standard elf routine.  */
>+  gld${EMULATION_NAME}_after_open ();
> }
>+
>+#ifndef TARGET_IS_elf32z80
>+static void
>+gld${EMULATION_NAME}_after_open (void)
>+{
>+}
>+#endif
>+
> /* --- \end{z80.em} */
> EOF
>+
>+LDEMUL_AFTER_OPEN=z80_after_open
>diff --git a/ld/emultempl/z80elf.em b/ld/emultempl/z80elf.em
>deleted file mode 100644
>index 2f755c673f..0000000000
>--- a/ld/emultempl/z80elf.em
>+++ /dev/null
>@@ -1,168 +0,0 @@
>-# This shell script emits C code -*- C -*-
>-# to keep track of the machine type of Z80 object files
>-# It does some substitutions.
>-#   Copyright (C) 2005-2019 Free Software Foundation, Inc.
>-# This file is part of the GNU Binutils.
>-#
>-# This program is free software; you can redistribute it and/or modify
>-# it under the terms of the GNU General Public License as published by
>-# the Free Software Foundation; either version 3 of the License, or
>-# (at your option) any later version.
>-#
>-# This program is distributed in the hope that it will be useful,
>-# but WITHOUT ANY WARRANTY; without even the implied warranty of
>-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>-# GNU General Public License for more details.
>-#
>-# You should have received a copy of the GNU General Public License
>-# along with this program; if not, write to the Free Software
>-# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
>-# MA 02110-1301, USA.
>-
>-fragment <<EOF
>-/* --- \begin{z80.em} */
>-
>-#include "elf/z80.h"
>-
>-static void
>-gld${EMULATION_NAME}_after_open (void);
>-
>-static int result_mach_type;
>-
>-struct z80_mach_info
>-{
>-  unsigned eflags;
>-  unsigned bfd_mach;
>-  const int *compat; /* back compatible machines */
>-};
>-
>-static const int
>-back_compat_z80[] = {bfd_mach_z80, -1};
>-
>-static const int
>-back_compat_z180[] = {bfd_mach_z180, bfd_mach_z80, -1};
>-
>-static const int
>-back_compat_ez80[] = {bfd_mach_ez80_z80, bfd_mach_z180, bfd_mach_z80, -1};
>-
>-static const struct z80_mach_info
>-z80_mach_info[] =
>-{
>-  { EF_Z80_MACH_Z80,      bfd_mach_z80,       NULL },
>-  { EF_Z80_MACH_Z80,      bfd_mach_z80strict, back_compat_z80 },
>-  { EF_Z80_MACH_Z80,      bfd_mach_z80full,   back_compat_z80 },
>-  { EF_Z80_MACH_Z180,     bfd_mach_z180,      back_compat_z80 },
>-  { EF_Z80_MACH_EZ80_Z80, bfd_mach_ez80_z80,  back_compat_z180 },
>-  { EF_Z80_MACH_EZ80_ADL, bfd_mach_ez80_adl,  back_compat_ez80 },
>-  { EF_Z80_MACH_Z80N,     bfd_mach_z80n,      back_compat_z80 },
>-  { EF_Z80_MACH_GBZ80,    bfd_mach_gbz80,     NULL },
>-  { EF_Z80_MACH_R800,     bfd_mach_r800,      back_compat_z80 }
>-};
>-
>-static const struct z80_mach_info *
>-z80_mach_info_by_eflags (unsigned int eflags)
>-{
>-  const struct z80_mach_info *p;
>-  const struct z80_mach_info *e;
>-
>-  eflags &= EF_Z80_MACH_MSK;
>-  p = &z80_mach_info[0];
>-  e = &z80_mach_info[sizeof(z80_mach_info)/sizeof(*z80_mach_info)];
>-  for (; p != e; ++p)
>-    if (eflags == p->eflags)
>-      return p;
>-  return NULL;
>-}
>-
>-static const struct z80_mach_info *
>-z80_mach_info_by_mach (unsigned int bfd_mach)
>-{
>-  const struct z80_mach_info *p;
>-  const struct z80_mach_info *e;
>-
>-  p = &z80_mach_info[0];
>-  e = &z80_mach_info[sizeof(z80_mach_info)/sizeof(*z80_mach_info)];
>-  for (; p != e; ++p)
>-    if (bfd_mach == p->bfd_mach)
>-      return p;
>-  return NULL;
>-}
>-
>-static const struct z80_mach_info *
>-z80_combine_mach (const struct z80_mach_info *m1,
>-		  const struct z80_mach_info *m2)
>-{
>-  int i;
>-  int mach;
>-  if (m1->compat != NULL)
>-    for (i = 0; (mach = m1->compat[i]) >= 0; ++i)
>-      if ((unsigned)mach == m2->bfd_mach)
>-	return m1;
>-  if (m2->compat != NULL)
>-    for (i = 0; (mach = m2->compat[i]) >= 0; ++i)
>-      if ((unsigned)mach == m1->bfd_mach)
>-	return m2;
>-  /* incompatible mach */
>-  return NULL;
>-}
>-
>-/* Set the machine type of the output file based on result_mach_type.  */
>-static void
>-z80_elf_after_open (void)
>-{
>-  const struct z80_mach_info *mach = NULL;
>-  bfd *abfd;
>-
>-  /* For now, make sure all object files are of the same architecture.
>-     We may try to merge object files with different architecture together.  */
>-  for (abfd = link_info.input_bfds; abfd != NULL; abfd = abfd->link.next)
>-    {
>-      const struct z80_mach_info *new_mach;
>-      new_mach = z80_mach_info_by_eflags (elf_elfheader (abfd)->e_flags);
>-      if (mach == NULL)
>-	mach = new_mach;
>-      else if (mach != new_mach)
>-	mach = z80_combine_mach (mach, new_mach);
>-      if (mach == NULL)
>-	einfo (_("%F%P: %pB: Instruction sets of object files incompatible\n"),
>-	       abfd);
>-    }
>-  if (mach != NULL)
>-    {
>-      bfd_set_arch_mach (link_info.output_bfd, bfd_arch_z80, mach->bfd_mach);
>-      result_mach_type = mach->bfd_mach;
>-    }
>-  else
>-    einfo (_("%F%P: %pB: Unknown machine type\n"),
>-	   abfd);
>-
>-  /* Call the standard elf routine.  */
>-  gld${EMULATION_NAME}_after_open ();
>-}
>-
>-static void
>-z80_elf_finish (void)
>-{
>-  bfd *abfd;
>-
>-  abfd = link_info.output_bfd;
>-
>-  if (bfd_get_flavour (abfd) == bfd_target_elf_flavour)
>-    {
>-      const struct z80_mach_info *info;
>-      info = z80_mach_info_by_mach (result_mach_type);
>-      if (info)
>-	{
>-	  elf_elfheader (abfd)->e_flags &= ~EF_Z80_MACH_MSK;
>-	  elf_elfheader (abfd)->e_flags |= info->eflags;
>-	}
>-    }
>-
>-  finish_default ();
>-}
>-
>-/* --- \end{z80.em} */
>-EOF
>-
>-LDEMUL_AFTER_OPEN=z80_elf_after_open
>-LDEMUL_FINISH=z80_elf_finish
>-- 
>2.17.1
>
>
>From 3be0f4268f29a3bfd615c06a92e593320b03609b Mon Sep 17 00:00:00 2001
>From: Sergey Belyashov <Sergey.Belyashov@gmail.com>
>Date: Mon, 3 Feb 2020 17:06:37 +0300
>Subject: [PATCH 5/7] Fix symbol naming in LD test pr21529
>
>---
> ld/testsuite/ld-unique/pr21529.s       | 8 ++++----
> ld/testsuite/ld-unique/unique.d        | 2 +-
> ld/testsuite/ld-unique/unique.s        | 6 +++---
> ld/testsuite/ld-unique/unique_empty.s  | 2 +-
> ld/testsuite/ld-unique/unique_shared.s | 6 +++---
> 5 files changed, 12 insertions(+), 12 deletions(-)
>
>diff --git a/ld/testsuite/ld-unique/pr21529.s b/ld/testsuite/ld-unique/pr21529.s
>index 4570635a05..fd09d61ba5 100644
>--- a/ld/testsuite/ld-unique/pr21529.s
>+++ b/ld/testsuite/ld-unique/pr21529.s
>@@ -1,8 +1,8 @@
>-	.type a, %gnu_unique_object
>-a:	.long 0
>-	.size a, .-a
>+	.type a_val, %gnu_unique_object
>+a_val:	.long 0
>+	.size a_val, .-a_val
> 
>         .type main,"function"
>         .global main
> main:
>-        .dc.a a
>+	.dc.a a_val
>diff --git a/ld/testsuite/ld-unique/unique.d b/ld/testsuite/ld-unique/unique.d
>index 73c939b49c..77422d5e5a 100644
>--- a/ld/testsuite/ld-unique/unique.d
>+++ b/ld/testsuite/ld-unique/unique.d
>@@ -5,5 +5,5 @@
> #...
>  *OS/ABI: +UNIX - GNU
> #...
>- *[0-9]+: +[0-9a-f]+ +[0-9]+ +OBJECT +UNIQUE +DEFAULT +[0-9]+ a
>+ *[0-9]+: +[0-9a-f]+ +[0-9]+ +OBJECT +UNIQUE +DEFAULT +[0-9]+ a_val
> #pass
>diff --git a/ld/testsuite/ld-unique/unique.s b/ld/testsuite/ld-unique/unique.s
>index 7477a694a2..cd5e64e60d 100644
>--- a/ld/testsuite/ld-unique/unique.s
>+++ b/ld/testsuite/ld-unique/unique.s
>@@ -1,6 +1,6 @@
>-	.type a, %gnu_unique_object
>-a:	.long 0
>-	.size a, .-a
>+	.type a_val, %gnu_unique_object
>+a_val:	.long 0
>+	.size a_val, .-a_val
> 
>         .type main,"function"
>         .global main
>diff --git a/ld/testsuite/ld-unique/unique_empty.s b/ld/testsuite/ld-unique/unique_empty.s
>index c4c52c2cda..4896641b50 100644
>--- a/ld/testsuite/ld-unique/unique_empty.s
>+++ b/ld/testsuite/ld-unique/unique_empty.s
>@@ -1,4 +1,4 @@
>         .type main,"function"
>         .global main
> main:
>-        .dc.a b
>+	.dc.a b_val
>diff --git a/ld/testsuite/ld-unique/unique_shared.s b/ld/testsuite/ld-unique/unique_shared.s
>index 8022291597..f1914f3393 100644
>--- a/ld/testsuite/ld-unique/unique_shared.s
>+++ b/ld/testsuite/ld-unique/unique_shared.s
>@@ -1,3 +1,3 @@
>-	.type b, %gnu_unique_object
>-b:	.long 0
>-	.size b, .-b
>+	.type b_val, %gnu_unique_object
>+b_val:	.long 0
>+	.size b_val, .-b_val
>-- 
>2.17.1
>
>
>From 953eda54f125d52b37b7180edc51044e0ed6e04e Mon Sep 17 00:00:00 2001
>From: Sergey Belyashov <Sergey.Belyashov@gmail.com>
>Date: Tue, 4 Feb 2020 11:40:20 +0300
>Subject: [PATCH 6/7] [Z80] Simplified GAS fix applying
>
>---
> gas/config/tc-z80.c | 105 +++++++++++++++++---------------------------
> 1 file changed, 41 insertions(+), 64 deletions(-)
>
>diff --git a/gas/config/tc-z80.c b/gas/config/tc-z80.c
>index b36f57ef94..c10876794b 100644
>--- a/gas/config/tc-z80.c
>+++ b/gas/config/tc-z80.c
>@@ -1139,7 +1139,6 @@ static void
> emit_byte (expressionS * val, bfd_reloc_code_real_type r_type)
> {
>   char *p;
>-  int lo, hi;
> 
>   if (r_type == BFD_RELOC_8)
>     {
>@@ -1158,15 +1157,12 @@ emit_byte (expressionS * val, bfd_reloc_code_real_type r_type)
>     }
>   else if (val->X_op == O_constant)
>     {
>-      lo = -128;
>-      hi = (BFD_RELOC_8 == r_type) ? 255 : 127;
>-
>-      if ((val->X_add_number < lo) || (val->X_add_number > hi))
>+      if ((val->X_add_number < -128) || (val->X_add_number >= 128))
> 	{
> 	  if (r_type == BFD_RELOC_Z80_DISP8)
>-	    as_bad (_("offset too large"));
>+	    as_bad (_("index overflow (%+ld)"), val->X_add_number);
> 	  else
>-	    as_warn (_("overflow"));
>+	    as_bad (_("offset overflow (%+ld)"), val->X_add_number);
> 	}
>     }
>   else
>@@ -3584,129 +3580,110 @@ end:
>   input_line_pointer = old_ptr;
> }
> 
>+static int
>+is_overflow (long value, unsigned bitsize)
>+{
>+  long fieldmask = (1 << bitsize) - 1;
>+  long signmask = ~fieldmask;
>+  long a = value & fieldmask;
>+  long ss = a & signmask;
>+  if (ss != 0 && ss != (signmask & fieldmask))
>+    return 1;
>+  return 0;
>+}
>+
> void
> md_apply_fix (fixS * fixP, valueT* valP, segT seg ATTRIBUTE_UNUSED)
> {
>-  long val = * (long *) valP;
>+  long val = (long)*valP;
>   char *p_lit = fixP->fx_where + fixP->fx_frag->fr_literal;
> 
>+  fixP->fx_done = (fixP->fx_addsy == NULL);
>+
>   switch (fixP->fx_r_type)
>     {
>     case BFD_RELOC_8_PCREL:
>-      if (fixP->fx_addsy)
>-        {
>-          fixP->fx_no_overflow = 1;
>-          fixP->fx_done = 0;
>-        }
>-      else
>-        {
>-	  fixP->fx_no_overflow = (-128 <= val && val < 128);
>-	  if (!fixP->fx_no_overflow)
>-            as_bad_where (fixP->fx_file, fixP->fx_line,
>-			  _("relative jump out of range"));
>-	  *p_lit++ = val;
>-          fixP->fx_done = 1;
>-        }
>-      break;
>-
>     case BFD_RELOC_Z80_DISP8:
>-      if (fixP->fx_addsy)
>-        {
>-          fixP->fx_no_overflow = 1;
>-          fixP->fx_done = 0;
>-        }
>-      else
>-        {
>-	  fixP->fx_no_overflow = (-128 <= val && val < 128);
>-	  if (!fixP->fx_no_overflow)
>-            as_bad_where (fixP->fx_file, fixP->fx_line,
>-			  _("index offset out of range"));
>-	  *p_lit++ = val;
>-          fixP->fx_done = 1;
>-        }
>+      if (fixP->fx_done && (val < -0x80 || val > 0x7f))
>+	as_bad_where (fixP->fx_file, fixP->fx_line,
>+		      _("8-bit signed offset out of range (%+ld)"), val);
>+      *p_lit++ = val;
>+      fixP->fx_no_overflow = 0;
>       break;
> 
>     case BFD_RELOC_Z80_BYTE0:
>       *p_lit++ = val;
>       fixP->fx_no_overflow = 1;
>-      if (fixP->fx_addsy == NULL)
>-        fixP->fx_done = 1;
>       break;
> 
>     case BFD_RELOC_Z80_BYTE1:
>       *p_lit++ = (val >> 8);
>       fixP->fx_no_overflow = 1;
>-      if (fixP->fx_addsy == NULL)
>-        fixP->fx_done = 1;
>       break;
> 
>     case BFD_RELOC_Z80_BYTE2:
>       *p_lit++ = (val >> 16);
>       fixP->fx_no_overflow = 1;
>-      if (fixP->fx_addsy == NULL)
>-        fixP->fx_done = 1;
>       break;
> 
>     case BFD_RELOC_Z80_BYTE3:
>       *p_lit++ = (val >> 24);
>       fixP->fx_no_overflow = 1;
>-      if (fixP->fx_addsy == NULL)
>-        fixP->fx_done = 1;
>       break;
> 
>     case BFD_RELOC_8:
>-      if (val > 255 || val < -128)
>-	as_warn_where (fixP->fx_file, fixP->fx_line, _("overflow"));
>+      if (fixP->fx_done && is_overflow(val, 8))
>+	as_warn_where (fixP->fx_file, fixP->fx_line,
>+		       _("8-bit overflow (%+ld)"), val);
>       *p_lit++ = val;
>-      fixP->fx_no_overflow = 1;
>-      if (fixP->fx_addsy == NULL)
>-	fixP->fx_done = 1;
>       break;
> 
>     case BFD_RELOC_Z80_WORD1:
>       *p_lit++ = (val >> 16);
>       *p_lit++ = (val >> 24);
>       fixP->fx_no_overflow = 1;
>-      if (fixP->fx_addsy == NULL)
>-        fixP->fx_done = 1;
>       break;
> 
>     case BFD_RELOC_Z80_WORD0:
>-    case BFD_RELOC_16:
>       *p_lit++ = val;
>       *p_lit++ = (val >> 8);
>       fixP->fx_no_overflow = 1;
>-      if (fixP->fx_addsy == NULL)
>-	fixP->fx_done = 1;
>+      break;
>+
>+    case BFD_RELOC_16:
>+      if (fixP->fx_done && is_overflow(val, 16))
>+	as_warn_where (fixP->fx_file, fixP->fx_line,
>+		       _("16-bit overflow (%+ld)"), val);
>+      *p_lit++ = val;
>+      *p_lit++ = (val >> 8);
>       break;
> 
>     case BFD_RELOC_24: /* Def24 may produce this.  */
>+      if (fixP->fx_done && is_overflow(val, 24))
>+	as_warn_where (fixP->fx_file, fixP->fx_line,
>+		       _("24-bit overflow (%+ld)"), val);
>       *p_lit++ = val;
>       *p_lit++ = (val >> 8);
>       *p_lit++ = (val >> 16);
>-      fixP->fx_no_overflow = 1;
>-      if (fixP->fx_addsy == NULL)
>-	fixP->fx_done = 1;
>       break;
> 
>     case BFD_RELOC_32: /* Def32 and .long may produce this.  */
>+      if (fixP->fx_done && is_overflow(val, 32))
>+	as_warn_where (fixP->fx_file, fixP->fx_line,
>+		       _("32-bit overflow (%+ld)"), val);
>       *p_lit++ = val;
>       *p_lit++ = (val >> 8);
>       *p_lit++ = (val >> 16);
>       *p_lit++ = (val >> 24);
>-      if (fixP->fx_addsy == NULL)
>-	fixP->fx_done = 1;
>       break;
> 
>     case BFD_RELOC_Z80_16_BE: /* Z80N PUSH nn instruction produce this.  */
>       *p_lit++ = val >> 8;
>       *p_lit++ = val;
>-      if (fixP->fx_addsy == NULL)
>-	fixP->fx_done = 1;
>       break;
> 
>     default:
>-      printf (_("md_apply_fix: unknown r_type 0x%x\n"), fixP->fx_r_type);
>+      printf (_("md_apply_fix: unknown reloc type 0x%x\n"), fixP->fx_r_type);
>       abort ();
>     }
> }
>-- 
>2.17.1
>
>
>From 6ad59812c532d7f6fa9707985b6a883255ae11df Mon Sep 17 00:00:00 2001
>From: Sergey Belyashov <Sergey.Belyashov@gmail.com>
>Date: Tue, 4 Feb 2020 11:44:23 +0300
>Subject: [PATCH 7/7] [Z80] More canonical function name
>
>---
> bfd/elf32-z80.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
>diff --git a/bfd/elf32-z80.c b/bfd/elf32-z80.c
>index 743cc7e5af..7b5da2f41d 100644
>--- a/bfd/elf32-z80.c
>+++ b/bfd/elf32-z80.c
>@@ -33,7 +33,7 @@
> /* Relocation functions.  */
> static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup
>   (bfd *, bfd_reloc_code_real_type);
>-static bfd_boolean z80_info_to_howto_rel
>+static bfd_boolean z80_info_to_howto_rela
>   (bfd *, arelent *, Elf_Internal_Rela *);
> 
> typedef struct {
>@@ -319,7 +319,7 @@ bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name)
> /* Set the howto pointer for an z80 ELF reloc.  */
> 
> static bfd_boolean
>-z80_info_to_howto_rel (bfd *abfd, arelent *cache_ptr, Elf_Internal_Rela *dst)
>+z80_info_to_howto_rela (bfd *abfd, arelent *cache_ptr, Elf_Internal_Rela *dst)
> {
>   enum
>     {
>@@ -504,9 +504,10 @@ z80_elf_16_be_reloc (bfd *abfd,
> #define TARGET_LITTLE_NAME		"elf32-z80"
> 
> #define elf_backend_can_gc_sections		1
>+#define elf_backend_stack_align			1
> 
>-#define elf_info_to_howto			NULL
>-#define elf_info_to_howto_rel			z80_info_to_howto_rel
>+#define elf_info_to_howto			z80_info_to_howto_rela
>+#define elf_info_to_howto_rel			z80_info_to_howto_rela
> #define elf_backend_final_write_processing	z80_elf_final_write_processing
> #define elf_backend_object_p			z80_elf_object_p
> #define bfd_elf32_bfd_is_local_label_name	z80_is_local_label_name
>-- 
>2.17.1
>

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