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(-)a/binutils/od-macho.c (-1 / +1 lines)
Lines 1686-1692 dump_unwind_encoding_x86 (unsigned int encoding, unsigned int sz, Link Here
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	unsigned int regs;
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	unsigned int regs;
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	char pfx = sz == 8 ? 'R' : 'E';
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	char pfx = sz == 8 ? 'R' : 'E';
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	regs = encoding & MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS;
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	regs = encoding & MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS
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	printf (" %cSP frame", pfx);
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	printf (" %cSP frame", pfx);
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	if (regs != 0)
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	if (regs != 0)
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	  {
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	  {
(-)a/cpu/or1kcommon.cpu (-1 / +1 lines)
Lines 170-176 Link Here
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   (SYS DCFGR    #x007 "Debug configuration register")
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   (SYS DCFGR    #x007 "Debug configuration register")
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   (SYS PCCFGR   #x008 "Performance counters configuration register")
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   (SYS PCCFGR   #x008 "Performance counters configuration register")
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   (SYS NPC      #x010 "Next program counter")
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   (SYS NPC      #x010 "Next program counter")
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   (SYS SR       #x011 "Supervision Regsiter")
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   (SYS SR       #x011 "Supervision Register")
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   (SYS PPC      #x012 "Previous program counter")
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   (SYS PPC      #x012 "Previous program counter")
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   (SYS FPCSR    #x014 "Floating point control status register")
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   (SYS FPCSR    #x014 "Floating point control status register")
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   (.unsplice
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   (.unsplice
(-)a/include/mach-o/unwind.h (+2 lines)
Lines 37-42 Link Here
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   %rbp-2040 (offset is encoded in offset bits * 8).  Registers saved are
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   %rbp-2040 (offset is encoded in offset bits * 8).  Registers saved are
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   encoded in registers bits, 3 bits per register.  */
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   encoded in registers bits, 3 bits per register.  */
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#define MACH_O_UNWIND_X86_64_MODE_RBP_FRAME  0x01000000
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#define MACH_O_UNWIND_X86_64_MODE_RBP_FRAME  0x01000000
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#define  MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS 0x00007FFF
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#define  MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS 0x00007FFF
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#define  MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS 0x00007FFF
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#define  MACH_O_UNWIND_X86_64_RBP_FRAME_OFFSET    0x00FF0000
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#define  MACH_O_UNWIND_X86_64_RBP_FRAME_OFFSET    0x00FF0000
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Lines 75-80 Link Here
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   %ebp-240 (offset is encoded in offset bits * 4).  Registers saved are
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   %ebp-240 (offset is encoded in offset bits * 4).  Registers saved are
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   encoded in registers bits, 3 bits per register.  */
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   encoded in registers bits, 3 bits per register.  */
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#define MACH_O_UNWIND_X86_MODE_EBP_FRAME  0x01000000
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#define MACH_O_UNWIND_X86_MODE_EBP_FRAME  0x01000000
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#define  MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS 0x00007FFF
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#define  MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS 0x00007FFF
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#define  MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS 0x00007FFF
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#define  MACH_O_UNWIND_X86_EBP_FRAME_OFFSET    0x00FF0000
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#define  MACH_O_UNWIND_X86_EBP_FRAME_OFFSET    0x00FF0000
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(-)a/opcodes/cr16-opc.c (-1 / +1 lines)
Lines 276-282 const inst cr16_instruction[] = Link Here
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  {"storm",  1, 0x16, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}},
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  {"storm",  1, 0x16, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}},
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  {"stormp", 1, 0x17, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}},
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  {"stormp", 1, 0x17, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}},
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 /* Processor Regsiter Manipulation instructions  */
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 /* Processor Register Manipulation instructions  */
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  /* opc16 reg, preg */
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  /* opc16 reg, preg */
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  {"lpr",  2, 0x00140, 12, NO_TYPE_INS, {{regr,0}, {pregr,4}}},
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  {"lpr",  2, 0x00140, 12, NO_TYPE_INS, {{regr,0}, {pregr,4}}},
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  /* opc16 regp, pregp */
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  /* opc16 regp, pregp */
(-)a/opcodes/hppa-dis.c (-1 / +1 lines)
Lines 425-431 print_insn_hppa (bfd_vma memaddr, disassemble_info *info) Link Here
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			fput_fp_reg (GET_FIELD (insn, 6, 10), info);
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			fput_fp_reg (GET_FIELD (insn, 6, 10), info);
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		      break;
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		      break;
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		      /* 'fA' will not generate a space before the regsiter
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		      /* 'fA' will not generate a space before the register
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			 name.  Normally that is fine.  Except that it
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			 name.  Normally that is fine.  Except that it
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			 causes problems with xmpyu which has no FP format
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			 causes problems with xmpyu which has no FP format
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			 completer.  */
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			 completer.  */
(-)a/sim/ppc/e500_registers.h (-1 / +1 lines)
Lines 28-34 enum { Link Here
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  msr_e500_spu_enable = BIT(38)
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  msr_e500_spu_enable = BIT(38)
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};
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};
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/* E500 regsiters.  */
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/* E500 registers.  */
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enum
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enum
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  {
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  {
(-)a/sim/ppc/ppc-instructions (-2 / +1 lines)
Lines 734-740 void::model-function::ppc_insn_to_spr:itable_index index, model_data *model_ptr, Link Here
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	busy_ptr->nr_writebacks = 1;
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	busy_ptr->nr_writebacks = 1;
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	TRACE(trace_model,("Making register %s busy.\n", spr_name(nSPR)));
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	TRACE(trace_model,("Making register %s busy.\n", spr_name(nSPR)));
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# Schedule a MFCR instruction that moves the CR into an integer regsiter
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# Schedule a MFCR instruction that moves the CR into an integer register
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void::model-function::ppc_insn_mfcr:itable_index index, model_data *model_ptr, unsigned32 int_mask
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void::model-function::ppc_insn_mfcr:itable_index index, model_data *model_ptr, unsigned32 int_mask
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	const unsigned32 cr_mask = 0xff;
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	const unsigned32 cr_mask = 0xff;
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	model_busy *busy_ptr;
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	model_busy *busy_ptr;
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- 

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