The Principles of Operation manuals lists 35 instruction formats where some of the formats have multiple variants. For the ‘.insn’ pseudo directive the assembler recognizes some of the formats. Typically, the most general variant of the instruction format is used by the ‘.insn’ directive.
The following table lists the abbreviations used in the table of instruction formats:
OpCode / OpCd | Part of the op code. |
Bx | Base register number for operand x. |
Dx | Displacement for operand x. |
DLx | Displacement lower 12 bits for operand x. |
DHx | Displacement higher 8-bits for operand x. |
Rx | Register number for operand x. |
Xx | Index register number for operand x. |
Ix | Signed immediate for operand x. |
Ux | Unsigned immediate for operand x. |
An instruction is two, four, or six bytes in length and must be aligned on a 2 byte boundary. The first two bits of the instruction specify the length of the instruction, 00 indicates a two byte instruction, 01 and 10 indicates a four byte instruction, and 11 indicates a six byte instruction.
The following table lists the s390 instruction formats that are available with the ‘.insn’ pseudo directive:
E format+-------------+ | OpCode | +-------------+ 0 15
RI format: <insn> R1,I2+--------+----+----+------------------+ | OpCode | R1 |OpCd| I2 | +--------+----+----+------------------+ 0 8 12 16 31
RIE format: <insn> R1,R3,I2+--------+----+----+------------------+--------+--------+ | OpCode | R1 | R3 | I2 |////////| OpCode | +--------+----+----+------------------+--------+--------+ 0 8 12 16 32 40 47
RIL format: <insn> R1,I2+--------+----+----+------------------------------------+ | OpCode | R1 |OpCd| I2 | +--------+----+----+------------------------------------+ 0 8 12 16 47
RILU format: <insn> R1,U2+--------+----+----+------------------------------------+ | OpCode | R1 |OpCd| U2 | +--------+----+----+------------------------------------+ 0 8 12 16 47
RIS format: <insn> R1,I2,M3,D4(B4)+--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 36 47
RR format: <insn> R1,R2+--------+----+----+ | OpCode | R1 | R2 | +--------+----+----+ 0 8 12 15
RRE format: <insn> R1,R2+------------------+--------+----+----+ | OpCode |////////| R1 | R2 | +------------------+--------+----+----+ 0 16 24 28 31
RRF format: <insn> R1,R2,R3,M4+------------------+----+----+----+----+ | OpCode | R3 | M4 | R1 | R2 | +------------------+----+----+----+----+ 0 16 20 24 28 31
RRS format: <insn> R1,R2,M3,D4(B4)+--------+----+----+----+-------------+----+----+--------+ | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode | +--------+----+----+----+-------------+----+----+--------+ 0 8 12 16 20 32 36 40 47
RS format: <insn> R1,R3,D2(B2)+--------+----+----+----+-------------+ | OpCode | R1 | R3 | B2 | D2 | +--------+----+----+----+-------------+ 0 8 12 16 20 31
RSE format: <insn> R1,R3,D2(B2)+--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | R3 | B2 | D2 |////////| OpCode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 40 47
RSI format: <insn> R1,R3,I2+--------+----+----+------------------------------------+ | OpCode | R1 | R3 | I2 | +--------+----+----+------------------------------------+ 0 8 12 16 47
RSY format: <insn> R1,R3,D2(B2)+--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 40 47
RX format: <insn> R1,D2(X2,B2)+--------+----+----+----+-------------+ | OpCode | R1 | X2 | B2 | D2 | +--------+----+----+----+-------------+ 0 8 12 16 20 31
RXE format: <insn> R1,D2(X2,B2)+--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | X2 | B2 | D2 |////////| OpCode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 40 47
RXF format: <insn> R1,R3,D2(X2,B2)+--------+----+----+----+-------------+----+---+--------+ | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode | +--------+----+----+----+-------------+----+---+--------+ 0 8 12 16 20 32 36 40 47
RXY format: <insn> R1,D2(X2,B2)+--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 36 40 47
S format: <insn> D2(B2)+------------------+----+-------------+ | OpCode | B2 | D2 | +------------------+----+-------------+ 0 16 20 31
SI format: <insn> D1(B1),I2+--------+---------+----+-------------+ | OpCode | I2 | B1 | D1 | +--------+---------+----+-------------+ 0 8 16 20 31
SIY format: <insn> D1(B1),U2+--------+---------+----+-------------+--------+--------+ | OpCode | I2 | B1 | DL1 | DH1 | OpCode | +--------+---------+----+-------------+--------+--------+ 0 8 16 20 32 36 40 47
SIL format: <insn> D1(B1),I2+------------------+----+-------------+-----------------+ | OpCode | B1 | D1 | I2 | +------------------+----+-------------+-----------------+ 0 16 20 32 47
SS format: <insn> D1(R1,B1),D2(B3),R3+--------+----+----+----+-------------+----+------------+ | OpCode | R1 | R3 | B1 | D1 | B2 | D2 | +--------+----+----+----+-------------+----+------------+ 0 8 12 16 20 32 36 47
SSE format: <insn> D1(B1),D2(B2)+------------------+----+-------------+----+------------+ | OpCode | B1 | D1 | B2 | D2 | +------------------+----+-------------+----+------------+ 0 8 12 16 20 32 36 47
SSF format: <insn> D1(B1),D2(B2),R3+--------+----+----+----+-------------+----+------------+ | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 | +--------+----+----+----+-------------+----+------------+ 0 8 12 16 20 32 36 47
VRV format: <insn> V1,D2(V2,B2),M3+--------+----+----+----+-------------+----+------------+ | OpCode | V1 | V2 | B2 | D2 | M3 | Opcode | +--------+----+----+----+-------------+----+------------+ 0 8 12 16 20 32 36 47
VRI format: <insn> V1,V2,I3,M4,M5+--------+----+----+-------------+----+----+------------+ | OpCode | V1 | V2 | I3 | M5 | M4 | Opcode | +--------+----+----+-------------+----+----+------------+ 0 8 12 16 28 32 36 47
VRX format: <insn> V1,D2(R2,B2),M3+--------+----+----+----+-------------+----+------------+ | OpCode | V1 | R2 | B2 | D2 | M3 | Opcode | +--------+----+----+----+-------------+----+------------+ 0 8 12 16 20 32 36 47
VRS format: <insn> R1,V3,D2(B2),M4+--------+----+----+----+-------------+----+------------+ | OpCode | R1 | V3 | B2 | D2 | M4 | Opcode | +--------+----+----+----+-------------+----+------------+ 0 8 12 16 20 32 36 47
VRR format: <insn> V1,V2,V3,M4,M5,M6+--------+----+----+----+---+----+----+----+------------+ | OpCode | V1 | V2 | V3 |///| M6 | M5 | M4 | Opcode | +--------+----+----+----+---+----+----+----+------------+ 0 8 12 16 24 28 32 36 47
VSI format: <insn> V1,D2(B2),I3+--------+---------+----+-------------+----+------------+ | OpCode | I3 | B2 | D2 | V1 | Opcode | +--------+---------+----+-------------+----+------------+ 0 8 16 20 32 36 47
For the complete list of all instruction format variants see the Principles of Operation manuals.