The following table lists the custom (vendor-defined) RISC-V extensions supported and provides the location of their publicly-released documentation:
The Xcvmac extension provides instructions for multiply-accumulate operations.
It is documented in https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
The Xcvalu extension provides instructions for general ALU operations.
It is documented in https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
The XTheadBa extension provides instructions for address calculations.
It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.
The XTheadBb extension provides instructions for basic bit-manipulation
It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.
The XTheadBs extension provides single-bit instructions.
It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.
The XTheadCmo extension provides instructions for cache management.
It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.
The XTheadCondMov extension provides instructions for conditional moves.
It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.
The XTheadFMemIdx extension provides floating-point memory operations.
It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.
The XTheadFmv extension provides access to the upper 32 bits of a doulbe-precision floating point register.
It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf.
The XTheadInt extension provides access to ISR stack management instructions.
It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf.
The XTheadMac extension provides multiply-accumulate instructions.
It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.
The XTheadMemIdx extension provides GPR memory operations.
It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.
The XTheadMemPair extension provides two-GP-register memory operations.
It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.
The XTheadSync extension provides instructions for multi-processor synchronization.
It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.
The XTheadVector extension provides instructions for thead vector.
It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf.
The XTheadZvamo extension is a subextension of the XTheadVector extension, and it provides AMO instructions for the T-Head VECTOR vendor extension.
It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf.
XVentanaCondOps extension provides instructions for branchless sequences that perform conditional arithmetic, conditional bitwise-logic, and conditional select operations.
It is documented in https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf.
The XSfVcp (VCIX) extension provides flexible instructions for extending vector coprocessor. To accelerate performance, system designers may use VCIX as a low-latency, high-throughput interface to a coprocessor.
It is documented in https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf.