9.15.5 Register Naming

Register operands are always prefixed with `%'. The 80386 registers consist of

• the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx', `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp' (the stack pointer).
• the 8 16-bit low-ends of these: `%ax', `%bx', `%cx', `%dx', `%di', `%si', `%bp', and `%sp'.
• the 8 8-bit registers: `%ah', `%al', `%bh', `%bl', `%ch', `%cl', `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax', `%bx', `%cx', and `%dx')
• the 6 section registers `%cs' (code section), `%ds' (data section), `%ss' (stack section), `%es', `%fs', and `%gs'.
• the 5 processor control registers `%cr0', `%cr2', `%cr3', `%cr4', and `%cr8'.
• the 6 debug registers `%db0', `%db1', `%db2', `%db3', `%db6', and `%db7'.
• the 2 test registers `%tr6' and `%tr7'.
• the 8 floating point register stack `%st' or equivalently `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)', `%st(6)', and `%st(7)'. These registers are overloaded by 8 MMX registers `%mm0', `%mm1', `%mm2', `%mm3', `%mm4', `%mm5', `%mm6' and `%mm7'.
• the 8 128-bit SSE registers registers `%xmm0', `%xmm1', `%xmm2', `%xmm3', `%xmm4', `%xmm5', `%xmm6' and `%xmm7'.

The AMD x86-64 architecture extends the register set by:

• enhancing the 8 32-bit registers to 64-bit: `%rax' (the accumulator), `%rbx', `%rcx', `%rdx', `%rdi', `%rsi', `%rbp' (the frame pointer), `%rsp' (the stack pointer)
• the 8 extended registers `%r8'–`%r15'.
• the 8 32-bit low ends of the extended registers: `%r8d'–`%r15d'.
• the 8 16-bit low ends of the extended registers: `%r8w'–`%r15w'.
• the 8 8-bit low ends of the extended registers: `%r8b'–`%r15b'.
• the 4 8-bit registers: `%sil', `%dil', `%bpl', `%spl'.
• the 8 debug registers: `%db8'–`%db15'.
• the 8 128-bit SSE registers: `%xmm8'–`%xmm15'.

With the AVX extensions more registers were made available:

• the 16 256-bit SSE `%ymm0'–`%ymm15' (only the first 8 available in 32-bit mode). The bottom 128 bits are overlaid with the `xmm0'–`xmm15' registers.

The AVX2 extensions made in 64-bit mode more registers available:

• the 16 128-bit registers `%xmm16'–`%xmm31' and the 16 256-bit registers `%ymm16'–`%ymm31'.

The AVX512 extensions added the following registers:

• the 32 512-bit registers `%zmm0'–`%zmm31' (only the first 8 available in 32-bit mode). The bottom 128 bits are overlaid with the `%xmm0'–`%xmm31' registers and the first 256 bits are overlaid with the `%ymm0'–`%ymm31' registers.
• the 8 mask registers `%k0'–`%k7'.