4.3 ld and the Motorola 68HC11 and 68HC12 families

4.3.1 Linker Relaxation

For the Motorola 68HC11, ld can perform these global optimizations when you specify the `--relax' command-line option.

relaxing address modes

ld finds all jsr and jmp instructions whose targets are within eight bits, and turns them into eight-bit program-counter relative bsr and bra instructions, respectively.

ld also looks at all 16-bit extended addressing modes and transforms them in a direct addressing mode when the address is in page 0 (between 0 and 0x0ff).

relaxing gcc instruction group

When gcc is called with -mrelax, it can emit group of instructions that the linker can optimize to use a 68HC11 direct addressing mode. These instructions consists of bclr or bset instructions.

4.3.2 Trampoline Generation

For 68HC11 and 68HC12, ld can generate trampoline code to call a far function using a normal jsr instruction. The linker will also change the relocation to some far function to use the trampoline address instead of the function address. This is typically the case when a pointer to a function is taken. The pointer will in fact point to the function trampoline.

The `--pic-veneer' switch makes the linker use PIC sequences for ARM/Thumb interworking veneers, even if the rest of the binary is not PIC. This avoids problems on uClinux targets where `--emit-relocs' is used to generate relocatable binaries.