as may be told to assemble for a particular CPU
(sub-)architecture with the
.arch cpu_type directive. This
directive enables a warning when gas detects an instruction that is not
supported on the CPU specified. The choices for cpu_type are:
|.mmx .sse .sse2 .3dnow
Apart from the warning, there are only two other effects on
as operation; Firstly, if you specify a CPU other than
i486, then shift by one instructions such as sarl $1, %eax
will automatically use a two byte opcode sequence. The larger three
byte opcode sequence is used on the 486 (and when no architecture is
specified) because it executes faster on the 486. Note that you can
explicitly request the two byte opcode by writing sarl %eax.
Secondly, if you specify i8086, i186, or i286,
and .code16 or .code16gcc then byte offset
conditional jumps will be promoted when necessary to a two instruction
sequence consisting of a conditional jump of the opposite sense around
an unconditional jump to the target.
Following the CPU architecture (but not a sub-architecture, which are those
starting with a dot), you may specify jumps or nojumps to
control automatic promotion of conditional jumps. jumps is the
default, and enables jump promotion; All external jumps will be of the long
variety, and file-local jumps will be promoted as necessary.
(see i386-Jumps) nojumps leaves external conditional jumps as
byte offset jumps, and warns about file-local conditional jumps that
Unconditional jumps are treated as for jumps.