8.17.1 M32R Options
The Renease M32R version of
as has a few machine
as can assemble code for several different members of the
Renesas M32R family. Normally the default is to assemble code for
the M32R microprocessor. This option may be used to change the default
to the M32RX microprocessor, which adds some more instructions to the
basic M32R instruction set, and some additional parameters to some of
the original instructions.
- This option changes the target processor to the the M32R2
- This option can be used to restore the assembler's default behaviour of
assembling for the M32R microprocessor. This can be useful if the
default has been changed by a previous command line option.
- This option tells the assembler to produce little-endian code and
data. The default is dependent upon how the toolchain was
- This is a synonum for -little.
- This option tells the assembler to produce big-endian code and
- This is a synonum for -big.
- This option specifies that the output of the assembler should be
marked as position-independent code (PIC).
- This option tells the assembler to attempts to combine two sequential
instructions into a single, parallel instruction, where it is legal to
- This option disables a previously enabled -parallel option.
- This option disables the support for the extended bit-field
instructions provided by the M32R2. If this support needs to be
re-enabled the -bitinst switch can be used to restore it.
- This option tells the assembler to attempt to optimize the
instructions that it produces. This includes filling delay slots and
converting sequential instructions into parallel ones. This option
as to produce warning messages when
questionable parallel instructions are encountered. This option is
enabled by default, but
gcc disables it when it invokes
as directly. Questionable instructions are those whoes
behaviour would be different if they were executed sequentially. For
example the code fragment mv r1, r2 || mv r3, r1 produces a
different result from mv r1, r2 \n mv r3, r1 since the former
moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1
- This is a shorter synonym for the -warn-explicit-parallel-conflicts
as not to produce warning messages when
questionable parallel instructions are encountered.
- This is a shorter synonym for the -no-warn-explicit-parallel-conflicts
- This option tells the assembler's to stop checking parallel
instructions for contraint violations. This ability is provided for
hardware vendors testing chip designs and should not be used under
- This option restores the assembler's default behaviour of checking
parallel instructions to detect constraint violations.
- This is a shorter synonym for the -ignore-parallel-conflicts
- This is a shorter synonym for the -no-ignore-parallel-conflicts
- This option tells the assembler to produce a warning message if a
.high pseudo op is encountered without a mathcing
pseudo op. The presence of such an unmatches pseudo op usually
indicates a programming error.
- Disables a previously enabled -warn-unmatched-high option.
- This is a shorter synonym for the -warn-unmatched-high option.
- This is a shorter synonym for the -no-warn-unmatched-high option.