This component models a variety of memory cache designs. Many common parameter groups (size, associativity, line-size, etc.) are exposed as individual component types in this family, e.g., hw-cache-2way/16kb/32/random, hw-cache-direct/1kb/16. The hw-cache-buffer-8 type is a special case containing just one 8-byte cache line.
This component models a memory cache suitable for use at different levels of the memory hierarchy. It provides a bus interface and connects to another bus, providing a transparent pass-through. In this documentation, "CPU" and "main memory" are synonymous for "upstream bus" and "downstream bus", as this is the most common usage (but not the only possible).
The parameters of the cache are a matter of configuration. At instantiation time, the following parameters are specified:
| Behaviors | |
|---|---|
| tag calculation |
The size of a tag is dynamically computed based on the line size. Unlike physical caches which economise on the number of tag bits to reduce hardware costs, the model uses a full address, but discards the redundant bits that can be inferred by a bytes position in the cache line. For example, a 32 (2^5) byte line uses 27 bits for the tag. |
| hash algorithm |
A simple hashing algorithm is used to select a set from a target address. The algorithm uses values from hash-bit-mask and hash-shift-amount to compute: These two values must be chosen carefully to ensure good cache utilisation. In particular, the "all-ones" value of mask should not exceed the number of sets in the cache. |
| misaligned accesses |
The component does not handle memory accesses that are not aligned on the natural boundary of the data being referenced. In such cases, the cache is bypassed and memory is accessed directly. |
| write strategy |
When a write is made to the cache, the write-through? attribute determines if the data will be simultaneously written to the memory. Otherwise, writes will only be made to the cache and will not be synchronised with main memory until the line is flushed due to line replacement or an explicit flush (see Flushing). In the case of a write miss, the write-allocate? attribute specifies the component's action. If this attribute is set to yes, then a miss will cause the missed line to be loaded into the cache in anticipation of future references. |
| prefetching |
The component supports prefetching of data into the cache by driving prefetch with an address. If, due to the line replacement policy, the prefetch cannot be performed, this operation has no effect. |
| flushing |
If dirty lines are flushed from the cache, the component will ensure that their contents are synchronized with main memory. Some architectures provide a facility for explicitly flushing a line to memory. For this purpose, the component provides flush which can be driven with an address. If the address falls on a line that is present and dirty, it will be flushed to memory and marked as not dirty. A line can be flushed and invalidated in one atomic operation by driving the flush-and-invalidate pin. The entire cache can be flushed by driving flush-all. |
| invalidating |
Lines in the cache that contain accurate contents are marked as valid. Some architectures provide a facility for explicitly marking a line as invalid so that future accesses will cause a new memory access. For this purpose, the component provides invalidate that can be driven with an address. If the address falls on a line that is present, it will be invalidated. No consideration is made for dirty lines, so a line should be flushed before being invalidated. A line can be flushed and invalidated in one atomic operation by driving the flush-and-invalidate pin. The entire cache can be invalidated by driving invalidate-all. |
| line locking |
The component supports locking lines in the cache to prevent them from being removed to accommodate more recently referenced lines. A line can be locked by driving lock with any address that falls on the line. Subsequently, a line can be unlocked by driving unlock. |
| memory latency |
The component models the effects of memory latency. The hit-latency and miss-latency values specify the cumulative latencies for hit and missed cache operations. Any misaligned accesses are penalised as if they are a miss. Cache line refills incur an additional latency, specified by the refill-latency attribute. |
| statistics gathering |
The component gathers statistics for a number of significant events and records them in read-only attributes. The collection of statistics may be disabled using collect-statistics?. |
| statistics reporting |
The component will write a summary report of the statistics it collects to standard error when report! is driven. The report-heading value, prepended to the report, allows reports from multiple caches to be distinguished. |
| SID Conventions | ||
|---|---|---|
| functional | supported | - |
| latency | supported | - |
Related components
This component is typically used as a cache between a CPU
and main memory. A sample configiruation fragment is:
new hw-cpu-arm7t cpu
new hw-cache-basic cache
connect-bus cpu insn-memory cache upstream
connect-bus cpu data-memory cache upstream
connect-bus cache downstream mem read-write-port
More extensive modeling of the memory hierarchy could be
achieved by daisy-chaining two cache component instances:
new hw-cpu-arm7t cpu
new hw-cache-basic l1-cache
new hw-cache-basic l2-cache
connect-bus cpu insn-memory l1-cache upstream
connect-bus cpu data-memory l1-cache upstream
connect-bus l1-cache downstream l2-cache upstream
connect-bus l2-cache downstream mem read-write-port
The cache can operate using virtual or physical addresses. This is determined by the location of the cache in the memory hierarchy. The cache can manage physical addresses by placing it "downstream" from an MMU or bus mapper (see hw-mapper-basic).
| pins | |||
|---|---|---|---|
| name | direction | legalvalues | behaviors |
| report! | in | - | statistics reporting |
| flush | in | 32-bit address | flushing |
| flush-all | in | any | flushing |
| flush-set | in | set index | flushing |
| invalidate | in | 32-bit address | invalidating |
| invalidate-all | in | any | invalidating |
| invalidate-set | in | set index | invalidating |
| flush-and-invalidate | in | 32-bit address | flushing, invalidating |
| flush-and-invalidate-set | in | set index | flushing, invalidating |
| prefetch | in | 32-bit address | prefetching |
| lock | in | 32-bit address | line locking |
| unlock | in | 32-bit address | line locking |
| buses | |||
|---|---|---|---|
| name | addresses | accesses | behaviors |
| upstream | unrestricted | unrestricted | bus traffic |
| accessors | ||
|---|---|---|
| name | accesses | behaviors |
| downstream | unrestricted | bus traffic |
Same as hw-cache-basic