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This is reported when the simulator detects that it is attempting to
deliver an interrupt to a processor that still has its MSR[RI] bit
clear.
Potential causes for this situtation are:
-
The interrupt handler code has failed to set the MSR[RI] bit after an
interrupt as been delivered.
-
External interrupts have been enabled before the interrupt handler has
set the MSR[RI] bit.
-
An interrupt handler has been incorrectly programmed and is causing an
exceptional condition.
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