PSIM includes (thanks to Michael Meissner) a detailed model of most of the PowerPC implementations to the functional unit level.
The PowerPC ISA defines SMP synchronizing instructions. This simulator implements a limited, but functional, subset of the PowerPC synchronization instructions behaviour. Programs that restrict their synchronization primitives to those that work with this functional sub-set (eg P() and V()) are able to run on the SMP version of PSIM.
People intending to use this system should study the code implementing the lwarx instruction.
PSIM implements the PowerPC's big and little (xor endian) modes and correctly simulates code that switches between these two modes.
In addition, psim can model a true little-endian machine.
PSIM includes a model of the UEA, VEA and OEA. This includes the time base registers (VEA) and HTAB and BATS (OEA).
In addition, a preliminary model of the 64 bit PowerPC architecture is implemented.
PSIM's internals are based around the concept of a Device Tree. This tree intentionally resembles that of the Device Tree found in OpenFirmware. PSIM is flexible enough to allow the user to fully configure this device tree (and consequently the hardware model) at run time.
PSIM's UEA (user) model includes emulation:
PSIM's OEA model includes emulation of either:
Preliminary support for floating point is included.