Index: sim/v850/ChangeLog
===================================================================
RCS file: /cvs/cvsfiles/devo/sim/v850/ChangeLog,v
retrieving revision 1.140
diff -u -5 -p -r1.140 ChangeLog
--- sim/v850/ChangeLog	1999/05/10 15:23:07	1.140
+++ sim/v850/ChangeLog	2000/05/08 14:04:33
@@ -1,5 +1,10 @@
+2000-04-14  Gary Thomas  <gthomas@redhat.com>
+
+	* v850.igen: Define 'br *' as illegal since this is the only
+	way to provide a breakpoint on some v850 family processors.
+
 1999-05-08  Felix Lee  <flee@cygnus.com>
 
 	* configure: Regenerated to track ../common/aclocal.m4 changes.
 	
 Tue Dec  1 17:25:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
Index: sim/v850/v850.igen
===================================================================
RCS file: /cvs/cvsfiles/devo/sim/v850/v850.igen,v
retrieving revision 1.23
diff -u -5 -p -r1.23 v850.igen
--- sim/v850/v850.igen	1999/02/01 11:21:52	1.23
+++ sim/v850/v850.igen	2000/05/08 14:04:33
@@ -142,14 +142,20 @@ rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI
 
 // Bcond
 ddddd,1011,ddd,cccc:III:::Bcond
 "b%s<cccc> <disp9>"
 {
-  int cond = condition_met (cccc);
-  if (cond)
-    nia = cia + disp9;
-  TRACE_BRANCH1 (cond);
+  int cond;
+  if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) {
+    // Special case - treat "br *" like illegal instruction
+    sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
+  } else {
+    cond = condition_met (cccc);
+    if (cond)
+      nia = cia + disp9;
+    TRACE_BRANCH1 (cond);
+  }
 }
 
 
 
 // BSH
@@ -1149,10 +1155,15 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI
 11111,000010,00000:I:::break
 {
   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
 }
 
+// True illegal instruction
+00000,111111,00000 + 00000,11111,100000:X:::ilgop
+{
+  sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
+}
 
 
 // DIVHN
 rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
 *v850ea
Index: gdb/ChangeLog
===================================================================
RCS file: /cvs/cvsfiles/devo/gdb/ChangeLog,v
retrieving revision 1.5130.2.2
diff -u -5 -p -r1.5130.2.2 ChangeLog
--- gdb/ChangeLog	2000/01/14 15:52:54	1.5130.2.2
+++ gdb/ChangeLog	2000/05/08 14:04:34
@@ -1,5 +1,11 @@
+2000-04-14  Gary Thomas  <gthomas@redhat.com>
+
+	* config/v850/tm-v850.h: Change breakpoint sequence to be
+	'br *' since there is no 16bit "illegal" instruction on this
+	processor.
+
 2000-01-14  Mark Salter  <msalter@cygnus.com>
 
 	* v850-tdep.c (v850_target_architecture_hook): Setup correct
 	machine id for disassembly.
 
Index: gdb/config/v850/tm-v850.h
===================================================================
RCS file: /cvs/cvsfiles/devo/gdb/config/v850/tm-v850.h,v
retrieving revision 1.26
diff -u -5 -p -r1.26 tm-v850.h
--- gdb/config/v850/tm-v850.h	1999/05/25 01:57:17	1.26
+++ gdb/config/v850/tm-v850.h	2000/05/08 14:04:36
@@ -79,11 +79,11 @@ extern char **v850_register_names;
 #define REGISTER_VIRTUAL_SIZE(REG) 4
 #define REGISTER_RAW_SIZE(REG) 4
 
 #define MAX_REGISTER_VIRTUAL_SIZE 4
 
-#define BREAKPOINT {0x40, 0xF8} /* little-ended */
+#define BREAKPOINT {0x85, 0x05} /* little-ended */
 
 #define FUNCTION_START_OFFSET 0
 
 #define DECR_PC_AFTER_BREAK 0