[binutils-gdb] arc: Add hardware loop detection
Shahab Vahedi
shahab@sourceware.org
Tue Aug 25 15:32:11 GMT 2020
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=fdd8731bd137e55453b501fa5404b5e6f60ddea0
commit fdd8731bd137e55453b501fa5404b5e6f60ddea0
Author: Shahab Vahedi <shahab@synopsys.com>
Date: Thu Jul 9 17:44:01 2020 +0200
arc: Add hardware loop detection
For ARC there are registers that are not part of a required set in XML
target descriptions by default, but are almost always present on ARC
targets and are universally exposed by the ptrace interface. Hardware
loop registers being one of them.
LP_START and LP_END auxiliary registers are hardware loop start and end.
Formally, they are optional, but it is hard to find an ARC configuration
that doesn't have them. They are always present in processors that can
run GNU/Linux. GDB needs to know about those registers to implement
proper software single stepping, since they affect what instruction
will be next.
This commit adds the code to check for the existance of "lp_start" and
"lp_end" in XML target descriptions. If they exist, then the function
reports that the target supports hardware loops.
gdb/ChangeLog:
* arc-tdep.c (arc_check_for_hardware_loop): New.
* arc-tdep.h (gdbarch_tdep): New field has_hw_loops.
gdb/doc/ChangeLog:
* gdb.texinfo (Synopsys ARC): Document LP_START, LP_END and BTA.
Diff:
---
gdb/ChangeLog | 5 +++++
gdb/arc-tdep.c | 39 +++++++++++++++++++++++++++++++++++----
gdb/arc-tdep.h | 3 +++
gdb/doc/ChangeLog | 4 ++++
gdb/doc/gdb.texinfo | 11 +++++++++--
5 files changed, 56 insertions(+), 6 deletions(-)
diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index c7e8cfd3bf6..2e97cdc061c 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,8 @@
+2020-08-25 Shahab Vahedi <shahab@synopsys.com>
+
+ * arc-tdep.c (arc_check_for_hardware_loop): New.
+ * arc-tdep.h (gdbarch_tdep): New field has_hw_loops.
+
2020-08-25 Shahab Vahedi <shahab@synopsys.com>
* arc-tdep.h: Include "gdbarch.h".
diff --git a/gdb/arc-tdep.c b/gdb/arc-tdep.c
index cb4941dec02..8b4e2857fb9 100644
--- a/gdb/arc-tdep.c
+++ b/gdb/arc-tdep.c
@@ -2041,6 +2041,35 @@ arc_check_tdesc_feature (struct tdesc_arch_data *tdesc_data,
return true;
}
+/* Check for the existance of "lp_start" and "lp_end" in target description.
+ If both are present, assume there is hardware loop support in the target.
+ This can be improved by looking into "lpc_size" field of "isa_config"
+ auxiliary register. */
+
+static bool
+arc_check_for_hw_loops (const struct target_desc *tdesc,
+ struct tdesc_arch_data *data)
+{
+ const auto feature_aux = tdesc_find_feature (tdesc, ARC_AUX_FEATURE_NAME);
+ const auto aux_regset = determine_aux_reg_feature_set ();
+
+ if (feature_aux == nullptr)
+ return false;
+
+ bool hw_loop_p = false;
+ const auto lp_start_name =
+ aux_regset->registers[ARC_LP_START_REGNUM - ARC_FIRST_AUX_REGNUM].names[0];
+ const auto lp_end_name =
+ aux_regset->registers[ARC_LP_END_REGNUM - ARC_FIRST_AUX_REGNUM].names[0];
+
+ hw_loop_p = tdesc_numbered_register (feature_aux, data,
+ ARC_LP_START_REGNUM, lp_start_name);
+ hw_loop_p &= tdesc_numbered_register (feature_aux, data,
+ ARC_LP_END_REGNUM, lp_end_name);
+
+ return hw_loop_p;
+}
+
/* Initialize target description for the ARC.
Returns true if input TDESC was valid and in this case it will assign TDESC
@@ -2163,13 +2192,15 @@ arc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
debug_printf ("arc: Architecture initialization.\n");
if (!arc_tdesc_init (info, &tdesc, &tdesc_data))
- return NULL;
+ return nullptr;
/* Allocate the ARC-private target-dependent information structure, and the
GDB target-independent information structure. */
- struct gdbarch_tdep *tdep = XCNEW (struct gdbarch_tdep);
+ gdb::unique_xmalloc_ptr<struct gdbarch_tdep> tdep
+ (XCNEW (struct gdbarch_tdep));
tdep->jb_pc = -1; /* No longjmp support by default. */
- struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep);
+ tdep->has_hw_loops = arc_check_for_hw_loops (tdesc, tdesc_data);
+ struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep.release ());
/* Data types. */
set_gdbarch_short_bit (gdbarch, 16);
@@ -2250,7 +2281,7 @@ arc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
It can override functions set earlier. */
gdbarch_init_osabi (info, gdbarch);
- if (tdep->jb_pc >= 0)
+ if (gdbarch_tdep (gdbarch)->jb_pc >= 0)
set_gdbarch_get_longjmp_target (gdbarch, arc_get_longjmp_target);
/* Disassembler options. Enforce CPU if it was specified in XML target
diff --git a/gdb/arc-tdep.h b/gdb/arc-tdep.h
index 5968abd4600..e752348a262 100644
--- a/gdb/arc-tdep.h
+++ b/gdb/arc-tdep.h
@@ -111,6 +111,9 @@ struct gdbarch_tdep
/* Offset to PC value in jump buffer. If this is negative, longjmp
support will be disabled. */
int jb_pc;
+
+ /* Whether target has hardware (aka zero-delay) loops. */
+ bool has_hw_loops;
};
/* Utility functions used by other ARC-specific modules. */
diff --git a/gdb/doc/ChangeLog b/gdb/doc/ChangeLog
index 6a81351282f..badf7ae10b5 100644
--- a/gdb/doc/ChangeLog
+++ b/gdb/doc/ChangeLog
@@ -1,3 +1,7 @@
+2020-08-25 Shahab Vahedi <shahab@synopsys.com>
+
+ * gdb.texinfo (Synopsys ARC): Document LP_START, LP_END and BTA.
+
2020-08-25 Shahab Vahedi <shahab@synopsys.com>
* gdb.texinfo (Synopsys ARC): Update the documentation for ARC
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index a4f5b787503..77c5d895053 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -45298,8 +45298,15 @@ Extension core registers @samp{r32} through @samp{r59} are optional and their
existence depends on the configuration. When debugging GNU/Linux applications,
i.e.@: user space debugging, these core registers are not available.
-The @samp{org.gnu.gdb.arc.aux} feature is required for all ARC targets. It
-should at least contain @samp{pc} and @samp{status32} registers.
+The @samp{org.gnu.gdb.arc.aux} feature is required for all ARC targets. Here
+is the list of registers pertinent to this feature:
+
+@itemize @minus
+@item
+mandatory: @samp{pc} and @samp{status32}.
+@item
+optional: @samp{lp_start}, @samp{lp_end}, and @samp{bta}.
+@end itemize
@node ARM Features
@subsection ARM Features
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