? bring209changesforward.txt Index: ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/ChangeLog,v retrieving revision 1.140 diff -u -b -w -r1.140 ChangeLog Index: devs/serial/powerpc/quicc/current/ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog,v retrieving revision 1.22 diff -u -b -w -r1.22 ChangeLog --- devs/serial/powerpc/quicc/current/ChangeLog 9 Feb 2004 16:33:42 -0000 1.22 +++ devs/serial/powerpc/quicc/current/ChangeLog 11 May 2004 00:15:56 -0000 @@ -1,8 +1,42 @@ +2004-05-10 Robert Chenault + + * src/quicc_smc_serial.h: Added two casts of (int) on calculations + involving CYGHWR_HAL_POWERPC_BOARD_SPEED. + + * src/quicc_smc_serial.c: Propagated Nick Garrett's 2004-01-08 + and 2003-12-18 changes (below) from 2.0.9 into the tip revision. + They are needed for PPP support and appear to have been missed + in the propagation sequence. + + * cdl/ser_quicc_smc.cdl: Propagated Nick Garrett's 2004-01-08 + and 2003-12-18 changes (below) from 2.0.9 into the tip revision. + They are needed for PPP support and appear to have been missed + in the propagation sequence. + 2004-01-24 Philip Soeberg * src/quicc_smc_serial.c(quicc_sxx_serial_init): SCC3 support for MPC8XX_823. +2004-01-08 Nick Garnett + + * src/quicc_smc_serial.c: Fixed bug in + quicc_scc_serial_config_port() that was resetting the RX engine + when it shouldn't. Made some other tidies. + + * cdl/ser_quicc_smc.cdl: Added serial testing parameters. Also + added requirements to set up the TTYs. While these will be fine + for the Adder boards, some more work will be needed to make them + generic. + +2003-12-18 Nick Garnett + + * src/quicc_smc_serial.c: Added support for RTS/CTS flow control. + + * cdl/ser_quicc_smc.cdl: Added implements statements for + CYGINT_IO_SERIAL_FLOW_CONTROL_HW and + CYGINT_IO_SERIAL_LINE_STATUS_HW to SCC3 driver. + 2003-10-13 Gary Thomas * src/quicc_smc_serial.c: Add some I/O barriers to make sure that Index: devs/serial/powerpc/quicc/current/cdl/ser_quicc_smc.cdl =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/serial/powerpc/quicc/current/cdl/ser_quicc_smc.cdl,v retrieving revision 1.9 diff -u -b -w -r1.9 ser_quicc_smc.cdl --- devs/serial/powerpc/quicc/current/cdl/ser_quicc_smc.cdl 23 Mar 2003 16:21:40 -0000 1.9 +++ devs/serial/powerpc/quicc/current/cdl/ser_quicc_smc.cdl 11 May 2004 00:15:56 -0000 @@ -10,6 +10,7 @@ ## This file is part of eCos, the Embedded Configurable Operating System. ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ## Copyright (C) 2002, 2003 Gary Thomas +## Copyright (C) 2003, 2004 eCosCentric Limited ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -91,6 +92,9 @@ QUICC/SMC port 1." } + requires CYGPKG_IO_SERIAL_TTY_TTY0 + requires { CYGDAT_IO_SERIAL_TTY_TTY0_DEV == "\"/dev/ser1\"" } + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BAUD { display "Baud rate for the PowerPC QUICC/SMC serial port 1" flavor data @@ -439,6 +443,9 @@ This option includes the serial device driver for the PowerPC QUICC/SCC port 3." + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + cdl_option CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_NAME { display "Device name for PowerPC QUICC/SCC serial port 3" flavor data @@ -448,6 +455,9 @@ QUICC/SCC port 3." } + requires CYGPKG_IO_SERIAL_TTY_TTY1 + requires { CYGDAT_IO_SERIAL_TTY_TTY1_DEV == "\"/dev/scc3\"" } + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_BAUD { display "Baud rate for the PowerPC QUICC/SCC serial port 3" flavor data @@ -509,6 +519,26 @@ This option specifies the number of input buffer packets to be used for the PowerPC QUICC/SCC port 3." } + + cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC_TESTING { + display "Testing parameters" + flavor bool + default_value 1 + no_define + active_if { CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC3 } + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"QUICC\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } + } # EOF ser_quicc_smc.cdl Index: devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c,v retrieving revision 1.18 diff -u -b -w -r1.18 quicc_smc_serial.c --- devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c 9 Feb 2004 16:33:43 -0000 1.18 +++ devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c 11 May 2004 00:15:56 -0000 @@ -10,6 +10,7 @@ // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. // Copyright (C) 2003 Gary Thomas +// Copyright (C) 2003, 2004 eCosCentric Limited // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -79,6 +80,8 @@ int txsize, rxsize; // Length of individual buffers cyg_interrupt serial_interrupt; cyg_handle_t serial_interrupt_handle; + unsigned short rts_port; // RTS bit port number + unsigned short rts_bit; // RTS bit mask } quicc_sxx_serial_info; static bool quicc_sxx_serial_init(struct cyg_devtab_entry *tab); @@ -479,7 +482,7 @@ // Disable channel during setup HAL_IO_BARRIER(); // Inforce I/O ordering regs->scc_gsmr_l = 0; - regs->scc_psmr = QUICC_SCC_PSMR_ASYNC | + regs->scc_psmr = scc_select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | scc_select_stop_bits[new_config->stop] | scc_select_parity[new_config->parity]; @@ -492,7 +495,7 @@ * Init Rx & Tx params for SCCX */ HAL_IO_BARRIER(); // Inforce I/O ordering - eppc->cp_cr = QUICC_CPM_CR_INIT_TXRX | scc_chan->channel | QUICC_CPM_CR_BUSY; + eppc->cp_cr = QUICC_CPM_CR_INIT_TX | scc_chan->channel | QUICC_CPM_CR_BUSY; HAL_IO_BARRIER(); // Inforce I/O ordering regs->scc_gsmr_l |= (QUICC_SCC_GSMR_L_Tx | QUICC_SCC_GSMR_L_Rx); // Enable Rx, Tx @@ -502,6 +505,36 @@ return true; } +static void quicc_scc_serial_rts( serial_channel *chan, cyg_bool on ) +{ + quicc_sxx_serial_info *scc_chan = (quicc_sxx_serial_info *)chan->dev_priv; + EPPC *eppc = eppc_base(); + + if (scc_chan->type == _SMC_CHAN) + return; + + switch( scc_chan->rts_port ) + { + case 1: // Port B + if( on ) + eppc->pip_pbdat &= ~scc_chan->rts_bit; + else + eppc->pip_pbdat |= scc_chan->rts_bit; + break; + + case 2: // Port C + if( on ) + eppc->pio_pcdat &= ~scc_chan->rts_bit; + else + eppc->pio_pcdat |= scc_chan->rts_bit; + break; + + case 0: // Port A -- no RTS lines here. + default: + break; + } +} + // Function to set up internal tables for device. static void quicc_scc_serial_init_info(quicc_sxx_serial_info *scc_chan, @@ -512,6 +545,7 @@ int RxBD, int RxNUM, int RxSIZE, cyg_uint8 *RxBUF, int portAmask, int portBmask, int portCmask, + unsigned short rts_port, unsigned short rts_bit, int port) { EPPC *eppc = eppc_base(); @@ -526,6 +560,22 @@ // Set up baud rate generator scc_chan->brg = _mpc8xx_allocate_brg(port); + // Set up RTS port parameters + scc_chan->rts_port = rts_port; + scc_chan->rts_bit = rts_bit; + + if( rts_port == 1 ) + { + eppc->pip_pbpar &= ~rts_bit; + eppc->pip_pbdir |= rts_bit; + } + else if( rts_port == 2 ) + { + eppc->pio_pcpar &= ~rts_bit; + eppc->pio_pcdir |= rts_bit; + eppc->pio_pcso &= ~rts_bit; + } + /* * Set up the PortA/B/C pins for UART operation. */ @@ -533,8 +583,8 @@ eppc->pio_padir &= ~portAmask; eppc->pio_paodr &= ~portAmask; - eppc->pio_pcdir &= portCmask; - eppc->pio_pcpar &= portCmask; + eppc->pio_pcdir &= ~portCmask; + eppc->pio_pcpar &= ~portCmask; eppc->pio_pcso |= portCmask; eppc->pip_pbpar |= portBmask; @@ -686,8 +736,9 @@ CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxSIZE, &quicc_scc1_rxbuf[0], 0x0003, // PortA mask - 0x1000, // PortB mask - 0x0800, // PortC mask + 0x0000, // PortB mask + 0x0010, // PortC mask + 1, 0x1000, // RTS on port B, bit 19 QUICC_CPM_SCC1 ); } @@ -708,8 +759,9 @@ CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxSIZE, &quicc_scc2_rxbuf[0], 0x000C, // PortA mask - 0x2000, // PortB mask - 0x0C00, // PortC mask + 0x0000, // PortB mask + 0x0040, // PortC mask + 1, 0x2000, // RTS on port B, bit 20 QUICC_CPM_SCC2 ); } @@ -732,11 +784,14 @@ #if defined(CYGHWR_HAL_POWERPC_MPC8XX_850) 0x0000, // PortA mask 0x00C0, // PortB mask - 0x0000, // PortC mask + 0x0100, // PortC mask +// 1, 0x4000, // RTS on port B, bit 17 + 2, 0x0004, // RTS on port C, bit 13 #elif defined(CYGHWR_HAL_POWERPC_MPC8XX_852T) 0x0030, // PortA mask 0x0000, // PortB mask - 0x0000, // PortC mask + 0x0100, // PortC mask + 2, 0x0004, // RTS on port C, bit 13 #elif defined(CYGHWR_HAL_POWERPC_MPC8XX_823) 0x0000, // PortA mask 0x00C0, // PortB mask @@ -764,6 +819,7 @@ quicc_smc_serial_config_port(chan, &chan->config, true); } else { quicc_scc_serial_config_port(chan, &chan->config, true); + quicc_scc_serial_rts( chan, true ); } if (cache_state) HAL_DCACHE_ENABLE(); @@ -893,6 +949,48 @@ return -EINVAL; } break; +#ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW + case CYG_IO_SET_CONFIG_SERIAL_HW_RX_FLOW_THROTTLE: + { + cyg_uint32 *f = (cyg_uint32 *)xbuf; + + if ( *len < sizeof(*f) ) + return -EINVAL; + + if ( chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_RX ) + { + quicc_scc_serial_rts( chan, !*f ); + } + } + break; + case CYG_IO_SET_CONFIG_SERIAL_HW_FLOW_CONFIG: + { + quicc_sxx_serial_info *scc_chan = (quicc_sxx_serial_info *)chan->dev_priv; + volatile struct scc_regs *regs = (volatile struct scc_regs *)scc_chan->ctl; + + // Flow control is only supported for SCC channels + if (scc_chan->type == _SMC_CHAN) + return -ENOSUPP; + + // Only RTS/CTS flow control is supported + if (0 != (chan->config.flags & (CYGNUM_SERIAL_FLOW_DSRDTR_RX | CYGNUM_SERIAL_FLOW_DSRDTR_TX))) + { + chan->config.flags &= (CYGNUM_SERIAL_FLOW_RTSCTS_RX | CYGNUM_SERIAL_FLOW_RTSCTS_TX); + return -ENOSUPP; + } + + // CTS flow control for TX + if (0 != (chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_TX)) { + // CTS flow control should be enabled. + regs->scc_psmr |= QUICC_SCC_PSMR_ASYNC; + } else { + // CTS flow control should be disabled. + regs->scc_psmr &= ~QUICC_SCC_PSMR_ASYNC; + } + + break; + } +#endif default: return -EINVAL; } Index: devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h,v retrieving revision 1.6 diff -u -b -w -r1.6 quicc_smc_serial.h --- devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h 8 Sep 2003 14:55:42 -0000 1.6 +++ devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h 11 May 2004 00:15:56 -0000 @@ -130,8 +130,8 @@ 0, // 230400 }; -#define UART_BITRATE(n) ((((CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/16)/n)-1) -#define UART_SLOW_BITRATE(n) ((CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/n)) +#define UART_BITRATE(n) ((((int)(CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/16)/n)-1) +#define UART_SLOW_BITRATE(n) ((int)(CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/n)) // Channel type select #define _SCC_CHAN 0