Index: var/current/cdl/hal_arm_at91.cdl =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/cdl/hal_arm_at91.cdl,v retrieving revision 1.7 diff -u -5 -p -r1.7 hal_arm_at91.cdl --- var/current/cdl/hal_arm_at91.cdl 13 Sep 2004 09:56:40 -0000 1.7 +++ var/current/cdl/hal_arm_at91.cdl 15 Sep 2004 10:40:59 -0000 @@ -83,6 +83,17 @@ cdl_package CYGPKG_HAL_ARM_AT91 { the main differences being the amount of on-chip SRAM, peripherals and their layout. This option allows the platform HALs to select the specific microcontroller being used." } + + cdl_option CYGHWR_HAL_ARM_AT91_FIQ { + display "handle FIQ as IRQ" + flavor bool + default_value 0 + description " + Enable this option if you need a default way to handle FIQ interrupts, + FIQs will be treated as IRQs with the highest priority" + + } + } Index: var/current/include/var_io.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/include/var_io.h,v retrieving revision 1.7 diff -u -5 -p -r1.7 var_io.h --- var/current/include/var_io.h 24 May 2004 08:41:47 -0000 1.7 +++ var/current/include/var_io.h 15 Sep 2004 10:41:00 -0000 @@ -638,8 +638,12 @@ #define AT91_WD_CR_RSTKEY 0x0000C071 #define AT91_WD_SR 0x0C #define AT91_WD_SR_WDOVF 0x00000001 +//============================================================================= +// FIQ interrupt line + +#define CYGNUM_HAL_INTERRUPT_FIQ 0 //----------------------------------------------------------------------------- // end of var_io.h #endif // CYGONCE_HAL_VAR_IO_H Index: var/current/src/at91_misc.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/src/at91_misc.c,v retrieving revision 1.8 diff -u -5 -p -r1.8 at91_misc.c --- var/current/src/at91_misc.c 12 Aug 2004 13:02:24 -0000 1.8 +++ var/current/src/at91_misc.c 15 Sep 2004 10:41:00 -0000 @@ -178,18 +178,27 @@ void hal_hardware_init(void) int hal_IRQ_handler(void) { cyg_uint32 irq_num; cyg_uint32 ivr; - +#ifdef CYGHWR_HAL_ARM_AT91_FIQ + cyg_uint32 ipr,imr; + HAL_READ_UINT32(AT91_AIC+AT91_AIC_IPR, ipr); + HAL_READ_UINT32(AT91_AIC+AT91_AIC_IMR, imr); + if(imr&ipr&0x1){ + HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_ICCR, 1); + return CYGNUM_HAL_INTERRUPT_FIQ; + } +#endif // Calculate active interrupt (updates ISR) HAL_READ_UINT32(AT91_AIC+AT91_AIC_IVR, ivr); HAL_READ_UINT32(AT91_AIC+AT91_AIC_ISR, irq_num); - + // No valid interrrupt source, treat as spurious interrupt - if (irq_num < CYGNUM_HAL_ISR_MIN || irq_num > CYGNUM_HAL_ISR_MAX) + // ISR return 0 in case of spurious interrupts,fiq or a valid IRQ line between 1-31 + if (irq_num == 0) irq_num = CYGNUM_HAL_INTERRUPT_NONE; return irq_num; }