This is the mail archive of the
newlib@sourceware.org
mailing list for the newlib project.
[PATCH 3/5] [ARM] Rename strlen to strlen-stub.c
- From: Marcus Shawcroft <marcus dot shawcroft at arm dot com>
- To: "newlib at sourceware dot org" <newlib at sourceware dot org>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>
- Date: Fri, 13 Nov 2015 12:05:14 +0000
- Subject: [PATCH 3/5] [ARM] Rename strlen to strlen-stub.c
- Authentication-results: sourceware.org; auth=none
In order to maintain consistency both within machine/arm and between
machine/arm and machine/aarch64, rename the 'c' stub to -stub.c.
Tested by building newlib and comparing libc.a binaries before and
after for all permutations of:
Architectures:
armv4 armv4t armv5 armv5t armv5te armv6 armv6j armv6k
armv6z armv6kz armv6t2 armv6-m armv6s-m armv7 armv7-a
armv7ve armv7-r armv7-m armv7e-m armv8-a iwmmxt iwmmxt2
ISAs:
thumb arm
Optimization Levels:
Os O2
Excluding:
armv6s-m -mthumb
armv6-m -mthumb
armv6zk -mthumb
armv6z -mthumb
armv6k -mthumb
armv6j -mthumb
OK ?
/Marcus
* libc/machine/arm/Makefile.am: Rename strlen.c to strlen-stub.c
* libc/machine/arm/Makefile.in: Regenerate.
* libc/machine/arm/strlen.c: Rename to...
* libc/machine/arm/strlen-stub.c: ... this.
diff --git a/newlib/ChangeLog b/newlib/ChangeLog
index fcc9154..7c2f38a 100644
--- a/newlib/ChangeLog
+++ b/newlib/ChangeLog
@@ -1,5 +1,12 @@
2015-11-13 Marcus Shawcroft <marcus.shawcroft@arm.com>
+ * libc/machine/arm/Makefile.am: Rename strlen.c to strlen-stub.c
+ * libc/machine/arm/Makefile.in: Regenerate.
+ * libc/machine/arm/strlen.c: Rename to...
+ * libc/machine/arm/strlen-stub.c: ... this.
+
+2015-11-13 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
* libc/machine/arm/Makefile.am: Drop STRLEN_SRC and STRLEN_OBJ.
Adding strlen.c.
* libc/machine/arm/configure.in (HAVE_THUMB1, OPT_SIZE): Remove.
diff --git a/newlib/libc/machine/arm/Makefile.am b/newlib/libc/machine/arm/Makefile.am
index d920e6e..212a3dc 100644
--- a/newlib/libc/machine/arm/Makefile.am
+++ b/newlib/libc/machine/arm/Makefile.am
@@ -16,7 +16,7 @@ lib_a_SOURCES += memchr-stub.c
lib_a_SOURCES += memchr.S
lib_a_SOURCES += memcpy-stub.c
lib_a_SOURCES += memcpy.S
-lib_a_SOURCES += strlen.c
+lib_a_SOURCES += strlen-stub.c
lib_a_CCASFLAGS=$(AM_CCASFLAGS)
lib_a_CFLAGS = $(AM_CFLAGS)
diff --git a/newlib/libc/machine/arm/Makefile.in b/newlib/libc/machine/arm/Makefile.in
index 87a3591..b43c422 100644
--- a/newlib/libc/machine/arm/Makefile.in
+++ b/newlib/libc/machine/arm/Makefile.in
@@ -78,7 +78,7 @@ am_lib_a_OBJECTS = lib_a-setjmp.$(OBJEXT) lib_a-access.$(OBJEXT) \
lib_a-aeabi_memset.$(OBJEXT) lib_a-aeabi_memset-soft.$(OBJEXT) \
lib_a-aeabi_memclr.$(OBJEXT) lib_a-memchr-stub.$(OBJEXT) \
lib_a-memchr.$(OBJEXT) lib_a-memcpy-stub.$(OBJEXT) \
- lib_a-memcpy.$(OBJEXT) lib_a-strlen.$(OBJEXT)
+ lib_a-memcpy.$(OBJEXT) lib_a-strlen-stub.$(OBJEXT)
lib_a_OBJECTS = $(am_lib_a_OBJECTS)
DEFAULT_INCLUDES = -I.@am__isrc@
depcomp =
@@ -209,7 +209,7 @@ lib_a_SOURCES = setjmp.S access.c strcmp.S strcpy.c strlen-armv7.S \
aeabi_memcpy.c aeabi_memcpy-armv7a.S aeabi_memmove.c \
aeabi_memmove-soft.S aeabi_memset.c aeabi_memset-soft.S \
aeabi_memclr.c memchr-stub.c memchr.S memcpy-stub.c memcpy.S \
- strlen.c
+ strlen-stub.c
lib_a_CCASFLAGS = $(AM_CCASFLAGS)
lib_a_CFLAGS = $(AM_CFLAGS)
ACLOCAL_AMFLAGS = -I ../../.. -I ../../../..
diff --git a/newlib/libc/machine/arm/strlen-stub.c b/newlib/libc/machine/arm/strlen-stub.c
new file mode 100644
index 0000000..9fb47ba
--- /dev/null
+++ b/newlib/libc/machine/arm/strlen-stub.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2008-2015 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ * products derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arm_asm.h"
+#include <_ansi.h>
+#include <string.h>
+#include <limits.h>
+
+#if defined __OPTIMIZE_SIZE__ || defined PREFER_SIZE_OVER_SPEED
+#if defined __thumb__ && !defined __thumb2__
+size_t
+strlen (const char* str)
+{
+ int scratch;
+ size_t len;
+ asm ("mov %0, #0\n"
+ "1:\n\t"
+ "ldrb %1, [%2, %0]\n\t"
+ "add %0, %0, #1\n\t"
+ "cmp %1, #0\n\t"
+ "bne 1b"
+ : "=&r" (len), "=&r" (scratch) : "r" (str) : "memory", "cc");
+ return len - 1;
+}
+
+#else
+size_t
+strlen (const char* str)
+{
+ int scratch;
+ const char* end;
+ asm ("1:\n\t"
+ "ldrb %1, [%0], #1\n\t"
+ "cmp %1, #0\n\t"
+ "bne 1b"
+ : "=&r" (end), "=&r" (scratch) : "0" (str) : "memory", "cc");
+ return end - str - 1;
+}
+#endif
+
+#else /* defined __OPTIMIZE_SIZE__ || defined PREFER_SIZE_OVER_SPEED */
+#if defined __thumb__ && ! defined __thumb2__
+#include "../../string/strlen.c"
+
+#elif defined _ISA_ARM_7 || defined __ARM_ARCH_6T2__
+ /* Implemented in strlen-armv7.S. */
+
+#else
+size_t __attribute__((naked))
+strlen (const char* str)
+{
+ asm ("len .req r0\n\t"
+ "data .req r3\n\t"
+ "addr .req r1\n\t"
+
+ "optpld r0\n\t"
+ /* Word-align address */
+ "bic addr, r0, #3\n\t"
+ /* Get adjustment for start ... */
+ "ands len, r0, #3\n\t"
+ "neg len, len\n\t"
+ /* First word of data */
+ "ldr data, [addr], #4\n\t"
+ /* Ensure bytes preceeding start ... */
+ "add ip, len, #4\n\t"
+ "mov ip, ip, asl #3\n\t"
+ "mvn r2, #0\n\t"
+ /* ... are masked out */
+#ifdef __thumb__
+ "itt ne\n\t"
+# ifdef __ARMEB__
+ "lslne r2, ip\n\t"
+# else
+ "lsrne r2, ip\n\t"
+# endif
+ "orrne data, data, r2\n\t"
+#else
+ "it ne\n\t"
+# ifdef __ARMEB__
+ "orrne data, data, r2, lsl ip\n\t"
+# else
+ "orrne data, data, r2, lsr ip\n\t"
+# endif
+#endif
+ /* Magic const 0x01010101 */
+#ifdef _ISA_ARM_7
+ "movw ip, #0x101\n\t"
+#else
+ "mov ip, #0x1\n\t"
+ "orr ip, ip, ip, lsl #8\n\t"
+#endif
+ "orr ip, ip, ip, lsl #16\n"
+
+ /* This is the main loop. We subtract one from each byte in
+ the word: the sign bit changes iff the byte was zero or
+ 0x80 -- we eliminate the latter case by anding the result
+ with the 1-s complement of the data. */
+ "1:\n\t"
+ /* test (data - 0x01010101) */
+ "sub r2, data, ip\n\t"
+ /* ... & ~data */
+ "bic r2, r2, data\n\t"
+ /* ... & 0x80808080 == 0? */
+ "ands r2, r2, ip, lsl #7\n\t"
+#ifdef _ISA_ARM_7
+ /* yes, get more data... */
+ "itt eq\n\t"
+ "ldreq data, [addr], #4\n\t"
+ /* and 4 more bytes */
+ "addeq len, len, #4\n\t"
+ /* If we have PLD, then unroll the loop a bit. */
+ "optpld addr, #8\n\t"
+ /* test (data - 0x01010101) */
+ "ittt eq\n\t"
+ "subeq r2, data, ip\n\t"
+ /* ... & ~data */
+ "biceq r2, r2, data\n\t"
+ /* ... & 0x80808080 == 0? */
+ "andeqs r2, r2, ip, lsl #7\n\t"
+#endif
+ "itt eq\n\t"
+ /* yes, get more data... */
+ "ldreq data, [addr], #4\n\t"
+ /* and 4 more bytes */
+ "addeq len, len, #4\n\t"
+ "beq 1b\n\t"
+#ifdef __ARMEB__
+ "tst data, #0xff000000\n\t"
+ "itttt ne\n\t"
+ "addne len, len, #1\n\t"
+ "tstne data, #0xff0000\n\t"
+ "addne len, len, #1\n\t"
+ "tstne data, #0xff00\n\t"
+ "it ne\n\t"
+ "addne len, len, #1\n\t"
+#else
+# ifdef _ISA_ARM_5
+ /* R2 is the residual sign bits from the above test. All we
+ need to do now is establish the position of the first zero
+ byte... */
+ /* Little-endian is harder, we need the number of trailing
+ zeros / 8 */
+# ifdef _ISA_ARM_7
+ "rbit r2, r2\n\t"
+ "clz r2, r2\n\t"
+# else
+ "rsb r1, r2, #0\n\t"
+ "and r2, r2, r1\n\t"
+ "clz r2, r2\n\t"
+ "rsb r2, r2, #31\n\t"
+# endif
+ "add len, len, r2, lsr #3\n\t"
+# else /* No CLZ instruction */
+ "tst data, #0xff\n\t"
+ "itttt ne\n\t"
+ "addne len, len, #1\n\t"
+ "tstne data, #0xff00\n\t"
+ "addne len, len, #1\n\t"
+ "tstne data, #0xff0000\n\t"
+ "it ne\n\t"
+ "addne len, len, #1\n\t"
+# endif
+#endif
+ "RETURN");
+}
+#endif
+#endif
diff --git a/newlib/libc/machine/arm/strlen.c b/newlib/libc/machine/arm/strlen.c
deleted file mode 100644
index 9fb47ba..0000000
--- a/newlib/libc/machine/arm/strlen.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * Copyright (c) 2008-2015 ARM Ltd
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the company may not be used to endorse or promote
- * products derived from this software without specific prior written
- * permission.
- *
- * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arm_asm.h"
-#include <_ansi.h>
-#include <string.h>
-#include <limits.h>
-
-#if defined __OPTIMIZE_SIZE__ || defined PREFER_SIZE_OVER_SPEED
-#if defined __thumb__ && !defined __thumb2__
-size_t
-strlen (const char* str)
-{
- int scratch;
- size_t len;
- asm ("mov %0, #0\n"
- "1:\n\t"
- "ldrb %1, [%2, %0]\n\t"
- "add %0, %0, #1\n\t"
- "cmp %1, #0\n\t"
- "bne 1b"
- : "=&r" (len), "=&r" (scratch) : "r" (str) : "memory", "cc");
- return len - 1;
-}
-
-#else
-size_t
-strlen (const char* str)
-{
- int scratch;
- const char* end;
- asm ("1:\n\t"
- "ldrb %1, [%0], #1\n\t"
- "cmp %1, #0\n\t"
- "bne 1b"
- : "=&r" (end), "=&r" (scratch) : "0" (str) : "memory", "cc");
- return end - str - 1;
-}
-#endif
-
-#else /* defined __OPTIMIZE_SIZE__ || defined PREFER_SIZE_OVER_SPEED */
-#if defined __thumb__ && ! defined __thumb2__
-#include "../../string/strlen.c"
-
-#elif defined _ISA_ARM_7 || defined __ARM_ARCH_6T2__
- /* Implemented in strlen-armv7.S. */
-
-#else
-size_t __attribute__((naked))
-strlen (const char* str)
-{
- asm ("len .req r0\n\t"
- "data .req r3\n\t"
- "addr .req r1\n\t"
-
- "optpld r0\n\t"
- /* Word-align address */
- "bic addr, r0, #3\n\t"
- /* Get adjustment for start ... */
- "ands len, r0, #3\n\t"
- "neg len, len\n\t"
- /* First word of data */
- "ldr data, [addr], #4\n\t"
- /* Ensure bytes preceeding start ... */
- "add ip, len, #4\n\t"
- "mov ip, ip, asl #3\n\t"
- "mvn r2, #0\n\t"
- /* ... are masked out */
-#ifdef __thumb__
- "itt ne\n\t"
-# ifdef __ARMEB__
- "lslne r2, ip\n\t"
-# else
- "lsrne r2, ip\n\t"
-# endif
- "orrne data, data, r2\n\t"
-#else
- "it ne\n\t"
-# ifdef __ARMEB__
- "orrne data, data, r2, lsl ip\n\t"
-# else
- "orrne data, data, r2, lsr ip\n\t"
-# endif
-#endif
- /* Magic const 0x01010101 */
-#ifdef _ISA_ARM_7
- "movw ip, #0x101\n\t"
-#else
- "mov ip, #0x1\n\t"
- "orr ip, ip, ip, lsl #8\n\t"
-#endif
- "orr ip, ip, ip, lsl #16\n"
-
- /* This is the main loop. We subtract one from each byte in
- the word: the sign bit changes iff the byte was zero or
- 0x80 -- we eliminate the latter case by anding the result
- with the 1-s complement of the data. */
- "1:\n\t"
- /* test (data - 0x01010101) */
- "sub r2, data, ip\n\t"
- /* ... & ~data */
- "bic r2, r2, data\n\t"
- /* ... & 0x80808080 == 0? */
- "ands r2, r2, ip, lsl #7\n\t"
-#ifdef _ISA_ARM_7
- /* yes, get more data... */
- "itt eq\n\t"
- "ldreq data, [addr], #4\n\t"
- /* and 4 more bytes */
- "addeq len, len, #4\n\t"
- /* If we have PLD, then unroll the loop a bit. */
- "optpld addr, #8\n\t"
- /* test (data - 0x01010101) */
- "ittt eq\n\t"
- "subeq r2, data, ip\n\t"
- /* ... & ~data */
- "biceq r2, r2, data\n\t"
- /* ... & 0x80808080 == 0? */
- "andeqs r2, r2, ip, lsl #7\n\t"
-#endif
- "itt eq\n\t"
- /* yes, get more data... */
- "ldreq data, [addr], #4\n\t"
- /* and 4 more bytes */
- "addeq len, len, #4\n\t"
- "beq 1b\n\t"
-#ifdef __ARMEB__
- "tst data, #0xff000000\n\t"
- "itttt ne\n\t"
- "addne len, len, #1\n\t"
- "tstne data, #0xff0000\n\t"
- "addne len, len, #1\n\t"
- "tstne data, #0xff00\n\t"
- "it ne\n\t"
- "addne len, len, #1\n\t"
-#else
-# ifdef _ISA_ARM_5
- /* R2 is the residual sign bits from the above test. All we
- need to do now is establish the position of the first zero
- byte... */
- /* Little-endian is harder, we need the number of trailing
- zeros / 8 */
-# ifdef _ISA_ARM_7
- "rbit r2, r2\n\t"
- "clz r2, r2\n\t"
-# else
- "rsb r1, r2, #0\n\t"
- "and r2, r2, r1\n\t"
- "clz r2, r2\n\t"
- "rsb r2, r2, #31\n\t"
-# endif
- "add len, len, r2, lsr #3\n\t"
-# else /* No CLZ instruction */
- "tst data, #0xff\n\t"
- "itttt ne\n\t"
- "addne len, len, #1\n\t"
- "tstne data, #0xff00\n\t"
- "addne len, len, #1\n\t"
- "tstne data, #0xff0000\n\t"
- "it ne\n\t"
- "addne len, len, #1\n\t"
-# endif
-#endif
- "RETURN");
-}
-#endif
-#endif
--
1.9.1