RE: Bug in strlen on old MIPS CPUs

["Steve Legg" <smlegg at googlemail dot com>]

> As for the actual condition, looking into the GCC sources I found this:
> 
> /* Which processor to schedule for.  Since there is no difference
> between
>    a R2000 and R3000 in terms of the scheduler, we collapse them into
>    just an R3000. [...] */
> 
> This means, there's no default definitions for the R2000, just for the
> R3000 ("R3000" and "_R3000").

Ah, okay - I didn't check that - that makes it a lot simpler then!  afaik the r2000 wasn't really used very much anyway (but possibly there are variants that were).
 
> So, apparently all CPUs with mips1 ISA with the exception of R3900 are
> affected, which just leaves R2000 and R3000.
> 
> Consequentially just using `#ifdef _R3000' should cover this situation,
> shouldn't it?

Yes, sounds like it should do - certainly all MIPS CPUs from R4000 upwards do not have the same problem (if they require a load delay then the pipeline has an interlock so you just get a one cycle stall).

Thanks,
Steve.