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Re: [patch, mips] Improved memset for MIPS
- From: Andrew Pinski <pinskia at gmail dot com>
- To: Steve Ellcey <sellcey at mips dot com>
- Cc: "Carlos O'Donell" <carlos at systemhalted dot org>, "Joseph S. Myers" <joseph at codesourcery dot com>, "Carlos O'Donell" <carlos at redhat dot com>, "libc-ports at sourceware dot org" <libc-ports at sourceware dot org>
- Date: Thu, 12 Dec 2013 16:22:55 -0800
- Subject: Re: [patch, mips] Improved memset for MIPS
- Authentication-results: sourceware.org; auth=none
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On Thu, Dec 12, 2013 at 4:14 PM, Steve Ellcey <email@example.com> wrote:
> On Thu, 2013-12-12 at 19:01 -0500, Carlos O'Donell wrote:
>> > I noticed this patch causes some performance regressions on Octeon due
>> > to having 128 byte cache lines.
>> > Changing PREFETCH_CHUNK/PREFETCH_FOR_STORE to assume 128 byte cache
>> > line gives us the performance back and improves over the original code
>> > at least 15%.
>> > That is:
>> > # define PREFETCH_CHUNK 128
>> > # define PREFETCH_FOR_STORE(chunk, reg) \
>> > pref PREFETCH_STORE_HINT, (chunk)*128(reg);
>> Submit a patch for that?
>> We have microbenchmarks now, but the next hardest
>> part is going to be archiving data by device so that
>> the community can help track performance and point
>> out regressions like this.
> Unless the change is under some kind of ifdef for Octeon changing this
> will probably slow down other MIPS chips. Most of them have 32 byte
> cache lines.
I think once ifunc support has been finalized, it would be useful to
build memset optimized for Octeon but until then I think it might be
best to disable the prefetching in the generic mips code.
> Steve Ellcey