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[PATCH v3] ARM: Improve armv7 memcpy performance.
- From: Will Newton <will dot newton at linaro dot org>
- To: libc-ports at sourceware dot org
- Cc: patches at linaro dot org
- Date: Mon, 09 Sep 2013 10:40:14 +0100
- Subject: [PATCH v3] ARM: Improve armv7 memcpy performance.
- Authentication-results: sourceware.org; auth=none
Only enter the aligned copy loop with buffers that can be 8-byte
aligned. This improves performance slightly on Cortex-A9 and
Cortex-A15 cores for large copies with buffers that are 4-byte
aligned but not 8-byte aligned.
2013-08-30 Will Newton <email@example.com>
* sysdeps/arm/armv7/multiarch/memcpy_impl.S: Tighten check
on entry to aligned copy loop to improve performance.
ports/sysdeps/arm/armv7/multiarch/memcpy_impl.S | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
Changes in v3:
- Fixed comments
diff --git a/ports/sysdeps/arm/armv7/multiarch/memcpy_impl.S b/ports/sysdeps/arm/armv7/multiarch/memcpy_impl.S
index 3decad6..330bb2d 100644
@@ -369,8 +369,8 @@ ENTRY(memcpy)
cfi_rel_offset (tmp2, 0)
- and tmp2, src, #3
- and tmp1, dst, #3
+ and tmp2, src, #7
+ and tmp1, dst, #7
cmp tmp1, tmp2
@@ -381,9 +381,9 @@ ENTRY(memcpy)
vmov.f32 s0, s0
- /* SRC and DST have the same mutual 32-bit alignment, but we may
+ /* SRC and DST have the same mutual 64-bit alignment, but we may
still need to pre-copy some bytes to get to natural alignment.
- We bring DST into full 64-bit alignment. */
+ We bring SRC and DST into full 64-bit alignment. */
lsls tmp2, dst, #29
rsbs tmp2, tmp2, #0