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Re: [PATCH 1/4] glibc: Perform rseq(2) registration at C startup and thread creation (v7)
- From: Mathieu Desnoyers <mathieu dot desnoyers at efficios dot com>
- To: Paul Burton <paul dot burton at mips dot com>
- Cc: Carlos O'Donell <codonell at redhat dot com>, Will Deacon <will dot deacon at arm dot com>, Boqun Feng <boqun dot feng at gmail dot com>, heiko carstens <heiko dot carstens at de dot ibm dot com>, gor <gor at linux dot ibm dot com>, schwidefsky <schwidefsky at de dot ibm dot com>, "Russell King, ARM Linux" <linux at armlinux dot org dot uk>, Benjamin Herrenschmidt <benh at kernel dot crashing dot org>, Paul Mackerras <paulus at samba dot org>, Michael Ellerman <mpe at ellerman dot id dot au>, carlos <carlos at redhat dot com>, Florian Weimer <fweimer at redhat dot com>, Joseph Myers <joseph at codesourcery dot com>, Szabolcs Nagy <szabolcs dot nagy at arm dot com>, libc-alpha <libc-alpha at sourceware dot org>, Thomas Gleixner <tglx at linutronix dot de>, Ben Maurer <bmaurer at fb dot com>, Peter Zijlstra <peterz at infradead dot org>, "Paul E. McKenney" <paulmck at linux dot vnet dot ibm dot com>, Dave Watson <davejwatson at fb dot com>, Paul Turner <pjt at google dot com>, Rich Felker <dalias at libc dot org>, linux-kernel <linux-kernel at vger dot kernel dot org>, linux-api <linux-api at vger dot kernel dot org>
- Date: Wed, 24 Apr 2019 11:05:42 -0400 (EDT)
- Subject: Re: [PATCH 1/4] glibc: Perform rseq(2) registration at C startup and thread creation (v7)
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----- On Apr 18, 2019, at 2:58 PM, Mathieu Desnoyers mathieu.desnoyers@efficios.com wrote:
> ----- On Apr 4, 2019, at 5:41 PM, Paul Burton paul.burton@mips.com wrote:
> [...]
>
>>> 2a. A uncommon TRAP hopefully with some immediate data encoded (maybe uncommon)
>>
>> Our break instruction has a 19b immediate in nanoMIPS (20b for microMIPS
>> & classic MIPS) so that could be something like:
>>
>> break 0x7273 # ASCII 'rs'
>>
>
> Hi Paul,
>
> I like this uncommon break instruction as signature choice.
>
> However, if I try to compile assembler with a break 0x7273 instruction
> with mips64 and mips32 toolchains (gcc version 8.2.0 (Ubuntu
> 8.2.0-1ubuntu2~18.04))
> I get:
>
> /tmp/ccVh9F7T.s: Assembler messages:
> /tmp/ccVh9F7T.s:24: Error: operand 1 out of range `break 0x7273'
>
> It works up to the value 0x3FF, which seems to use the top 10
> code bits:
>
> a: 03ff 0007 break 0x3ff
>
> Would a "break 0x350" be a good choice as well ?
>
> Any idea why 0x7273 is not accepted by my assembler ?
>
> I also tried crafting the assembler with values between 0x3FF and 0x7273
> in the 20 code bits. It seems fine from an objdump perspective:
>
> ".long 0x03FFFC7\n\t"
>
> generates:
>
> 10: 003f ffc7 break 0x3f,0x3ff
>
> What I don't understand is why the instruction generated by my
> toolchain ends with the last 6 bits "000111", whereas the mips32
> instruction set specifies break as ending with "001101" [1].
> What am I missing ?
>
> Also, the nanomips break code [2] has a completely different
> instruction layout. Should we use a different signature when
> compiling for nanomips ? What #ifdef should we use ? Do I
> need a special toolchain to generate nanomips binaries ?
Hi Paul, I'm still waiting for feedback on the MIPS front.
Meanwhile, I plan to use #define RSEQ_SIG 0x0350000d which maps to:
0350000d break 0x350
and use RSEQ_SIG in assembly with:
".word " __rseq_str(RSEQ_SIG) "\n\t"
on big and little endian MIPS, for MIPS32 and MIPS64, based on
code generated with gcc version 8.2.0 (Ubuntu 8.2.0-1ubuntu2~18.04).
Let me know if it needs to be tweaked.
Thanks,
Mathieu
>
> Thanks,
>
> Mathieu
>
> [1]
> http://hades.mech.northwestern.edu/images/1/16/MIPS32_Architecture_Volume_II-A_Instruction_Set.pdf
> [2]
> https://s3-eu-west-1.amazonaws.com/downloads-mips/I7200/I7200+product+launch/MIPS_nanomips32_ISA_TRM_01_01_MD01247.pdf
>
> --
> Mathieu Desnoyers
> EfficiOS Inc.
> http://www.efficios.com
--
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com