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Re: [PATCH][AArch64] Adjust writeback in non-zero memset

From: Siddhesh Poyarekar <siddhesh at gotplt dot org>
To: Wilco Dijkstra <Wilco dot Dijkstra at arm dot com>, 'GNU C Library' <libc-alpha at sourceware dot org>, Szabolcs Nagy <Szabolcs dot Nagy at arm dot com>
Cc: nd <nd at arm dot com>
Date: Fri, 16 Nov 2018 22:46:09 +0530
Subject: Re: [PATCH][AArch64] Adjust writeback in non-zero memset
References: <DB5PR08MB103042C88641FD9D3A04C3F983C40@DB5PR08MB1030.eurprd08.prod.outlook.com> <DB5PR08MB103082464EB664B31AFC5C5783C30@DB5PR08MB1030.eurprd08.prod.outlook.com> <83ddfdc0-a16e-2de7-f49e-695ed27e107b@gotplt.org> <DB5PR08MB1030C244B0823798AA01F8FF83DD0@DB5PR08MB1030.eurprd08.prod.outlook.com>

On 16/11/18 10:34 PM, Wilco Dijkstra wrote:

I ran it on Cortex-A72, and there isn't a performance difference on the memset bench
beyond measurement errors. On any out-of-order core address increments are
executed in parallel with loads/stores, ie. they have no measurable latency and so
their exact placement is irrelevant.


Thanks for the confirmation.  Looks OK to me.

Siddhesh

References:
- [PATCH][AArch64] Adjust writeback in non-zero memset
  - From: Wilco Dijkstra
- Re: [PATCH][AArch64] Adjust writeback in non-zero memset
  - From: Wilco Dijkstra
- Re: [PATCH][AArch64] Adjust writeback in non-zero memset
  - From: Siddhesh Poyarekar
- Re: [PATCH][AArch64] Adjust writeback in non-zero memset
  - From: Wilco Dijkstra

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