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On 10/19/2017 05:56 PM, Tulio Magno Quites Machado Filho wrote:
Or is the performance hit from avoiding the affected vector instructions not so severe that it would be an immediate concern for future silicon?The instructions Raji chose to use here do not impact the performance on current silicon and is not expected to impact future silicon as well.
Okay, this addresses my concern. Unfortunately, I don't feel confident to review the new implementation myself.
Thanks, Florian
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