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Re: [PATCH v3 10/28] arm64/sve: Low-level CPU setup
- From: Catalin Marinas <catalin dot marinas at arm dot com>
- To: Dave Martin <Dave dot Martin at arm dot com>
- Cc: linux-arm-kernel at lists dot infradead dot org, linux-arch at vger dot kernel dot org, Okamoto Takayuki <tokamoto at jp dot fujitsu dot com>, libc-alpha at sourceware dot org, Ard Biesheuvel <ard dot biesheuvel at linaro dot org>, Szabolcs Nagy <szabolcs dot nagy at arm dot com>, Will Deacon <will dot deacon at arm dot com>, Richard Sandiford <richard dot sandiford at arm dot com>, Alex Bennée <alex dot bennee at linaro dot org>, kvmarm at lists dot cs dot columbia dot edu
- Date: Wed, 11 Oct 2017 15:30:42 +0100
- Subject: Re: [PATCH v3 10/28] arm64/sve: Low-level CPU setup
- Authentication-results: sourceware.org; auth=none
- References: <1507660725-7986-1-git-send-email-Dave.Martin@arm.com> <1507660725-7986-11-git-send-email-Dave.Martin@arm.com>
On Tue, Oct 10, 2017 at 07:38:27PM +0100, Dave P Martin wrote:
> To enable the kernel to use SVE, SVE traps from EL1 to EL2 must be
> disabled. To take maximum advantage of the hardware, the full
> available vector length also needs to be enabled for EL1 by
> programming ZCR_EL2.LEN. (The kernel will program ZCR_EL1.LEN as
> required, but this cannot override the limit set by ZCR_EL2.)
>
> Traps from EL0 to EL1 are also left enabled by virtue of setting
> the relevant CPACR bit at its default (RES0) value.
>
> This patch makes the appropriate changes to the primary and
> secondary CPU initialisation code.
>
> Signed-off-by: Dave Martin <Dave.Martin@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>