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Re: [RFC PATCH 00/29] arm64: Scalable Vector Extension core support
- From: Szabolcs Nagy <szabolcs dot nagy at arm dot com>
- To: Florian Weimer <fweimer at redhat dot com>, Dave Martin <Dave dot Martin at arm dot com>
- Cc: <nd at arm dot com>, <libc-alpha at sourceware dot org>, Ard Biesheuvel <ard dot biesheuvel at linaro dot org>, Marc Zyngier <Marc dot Zyngier at arm dot com>, <gdb at sourceware dot org>, Yao Qi <qiyaoltc at gmail dot com>, <linux-arm-kernel at lists dot infradead dot org>, Alan Hayward <alan dot hayward at arm dot com>, Torvald Riegel <triegel at redhat dot com>, Christoffer Dall <christoffer dot dall at linaro dot org>
- Date: Mon, 5 Dec 2016 11:07:12 +0000
- Subject: Re: [RFC PATCH 00/29] arm64: Scalable Vector Extension core support
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On 05/12/16 10:44, Florian Weimer wrote:
>>> By the way, how is this implemented? Some of them overlap existing
>>> callee-saved registers.
>>
>> Basically, all the *new* state is caller-save.
>>
>> The Neon/FPSIMD regs V8-V15 are callee-save, so in the SVE view
>> Zn[bits 127:0] is callee-save for all n = 8..15.
>
> Are the extension parts of registers v8 to v15 used for argument passing?
>
> If not, we should be able to use the existing dynamic linker trampoline.
>
if sve arguments are passed to a function then it
has special call abi (which is probably not yet
documented), this call abi requires that such a
call does not go through plt to avoid requiring
sve aware libc.
same for tls access: the top part of sve regs have
to be saved by the caller before accessing tls so
the tlsdesc entry does not have to save them.
so current trampolines should be fine.