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Re: Malloc improvements
- From: Anton Blanchard <anton at au1 dot ibm dot com>
- To: Florian Weimer <fweimer at redhat dot com>
- Cc: "Carlos O'Donell" <carlos at redhat dot com>, Siddhesh Poyarekar <sid at reserved-bit dot com>, DJ Delorie <dj at redhat dot com>, libc-alpha at sourceware dot org, tuliom at linux dot vnet dot ibm dot com
- Date: Tue, 19 Jul 2016 22:03:31 +1000
- Subject: Re: Malloc improvements
- Authentication-results: sourceware.org; auth=none
- References: <20160712101010.6e6cfecb@kryten> <5a954ab2-d74c-867d-e427-ffae95389beb@redhat.com> <20160714214910.6727c439@kryten> <8b72c439-a9c3-4cfd-f9a1-f67836ea4795@redhat.com>
Hi Florian.
> x86_64 checks __libc_multiple_threads and avoids atomics if possible.
> Do you already do this in POWER?
x86 has CISCy instructions that do a local atomic increment/decrement,
and I suspect they use that in the single threaded case. We do not have
instructions like that on PowerPC, and it presents an issue for signals.
I think we got resistance when we suggested using load/add/store
instructions in single threaded mode on PowerPC because it made the
async signal situation somewhat worse. Of course malloc is not defined
to be async signal safe, and I bet there are places we fall apart today.
Perhaps we can revisit this now we have an unlocked per thread cache in
DJ's branch.
Anton