This is the mail archive of the libc-alpha@sourceware.org mailing list for the glibc project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[PATCH] x86: sysconf: use new cpuid.h header


This produces better code in the non-PIC case, and when using newer gcc
versions (as you can declare ebx as clobbered).  Since we require 4.6+,
and the nptl code already leverages cpuid.h, using it here should be OK.

2015-08-11  Mike Frysinger  <vapier@gentoo.org>

	* sysdeps/unix/sysv/linux/i386/sysconf.c: Include cpuid.h.
	(intel_check_word): Change inline cpuid asm to __cpuid_count and
	__cpuid.
	(handle_intel, handle_amd, __sysconf): Likewise.
---
 sysdeps/unix/sysv/linux/i386/sysconf.c | 25 +++++++------------------
 1 file changed, 7 insertions(+), 18 deletions(-)

diff --git a/sysdeps/unix/sysv/linux/i386/sysconf.c b/sysdeps/unix/sysv/linux/i386/sysconf.c
index 0b5a681..ab3edae 100644
--- a/sysdeps/unix/sysv/linux/i386/sysconf.c
+++ b/sysdeps/unix/sysv/linux/i386/sysconf.c
@@ -21,6 +21,7 @@
 #include <stdlib.h>
 #include <unistd.h>
 #include <hp-timing.h>
+#include <cpuid.h>
 
 static long int linux_sysconf (int name);
 
@@ -197,9 +198,7 @@ intel_check_word (int name, unsigned int value, bool *has_level_2,
 	  unsigned int round = 0;
 	  while (1)
 	    {
-	      asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
-			    : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
-			    : "0" (4), "2" (round));
+	      __cpuid_count (4, round, eax, ebx, ecx, edx);
 
 	      enum { null = 0, data = 1, inst = 2, uni = 3 } type = eax & 0x1f;
 	      if (type == null)
@@ -247,9 +246,7 @@ intel_check_word (int name, unsigned int value, bool *has_level_2,
 	      unsigned int ebx;
 	      unsigned int ecx;
 	      unsigned int edx;
-	      asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
-			    : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
-			    : "0" (1));
+	      __cpuid (1, eax, ebx, ecx, edx);
 
 	      unsigned int family = ((eax >> 20) & 0xff) + ((eax >> 8) & 0xf);
 	      unsigned int model = ((((eax >>16) & 0xf) << 4)
@@ -324,9 +321,7 @@ handle_intel (int name, unsigned int maxidx)
       unsigned int ebx;
       unsigned int ecx;
       unsigned int edx;
-      asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
-		    : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
-		    : "0" (2));
+      __cpuid (2, eax, ebx, ecx, edx);
 
       /* The low byte of EAX in the first round contain the number of
 	 rounds we have to make.  At least one, the one we are already
@@ -370,9 +365,7 @@ handle_amd (int name)
   unsigned int ebx;
   unsigned int ecx;
   unsigned int edx;
-  asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
-		: "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
-		: "0" (0x80000000));
+  __cpuid (0x80000000, eax, ebx, ecx, edx);
 
   if (name >= _SC_LEVEL3_CACHE_SIZE)
     return 0;
@@ -381,9 +374,7 @@ handle_amd (int name)
   if (eax < fn)
     return 0;
 
-  asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
-		: "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
-		: "0" (fn));
+  __cpuid (fn, eax, ebx, ecx, edx);
 
   if (name < _SC_LEVEL1_DCACHE_SIZE)
     {
@@ -485,9 +476,7 @@ __sysconf (int name)
   unsigned int ebx;
   unsigned int ecx;
   unsigned int edx;
-  asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
-		: "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
-		: "0" (0));
+  __cpuid (0, eax, ebx, ecx, edx);
 
   /* This spells out "GenuineIntel".  */
   if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
-- 
2.4.4


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]