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Re: [PATCH] powerpc: Spinlock optimization and cleanup
- From: Richard Henderson <rth at twiddle dot net>
- To: Adhemerval Zanella <azanella at linux dot vnet dot ibm dot com>, libc-alpha at sourceware dot org
- Date: Tue, 10 Mar 2015 08:34:47 -0700
- Subject: Re: [PATCH] powerpc: Spinlock optimization and cleanup
- Authentication-results: sourceware.org; auth=none
- References: <54EF91B2 dot 3020704 at linux dot vnet dot ibm dot com> <1425039649 dot 16367 dot 15 dot camel at triegel dot csb> <54F085D7 dot 2030002 at linux dot vnet dot ibm dot com>
On 02/27/2015 06:57 AM, Adhemerval Zanella wrote:
> We already have support for EH hint in LL/SC instruction for powerpc. The trick
> in this algorithm is it does not really fix in current atomic semantics we have
> so far, as '__arch_compare_and_exchange_val_32_acq' issues an 'isync' in either
> fail or succeed case. The trick in this case is just to emit the 'isync' just
> after the stcx. instruction. Basically the idea is to loop over checking
> when lock is release using default loads 'inside' the CAS-acquire. Suggestions?
This does sound like the two memory model inputs to the builtin
__atomic_compare_and_exchange_n: one for the succeed case and
one for the fail case.