This is the mail archive of the libc-alpha@sourceware.org mailing list for the glibc project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[PATCH][RFC] Fix SPARC atomic_write_barrier.


This patch changes SPARC write barriers to be just release barriers.  I
haven't tested this, so this is based on my understanding of the SPARC
memory model (TSO).

For a release barrier, we have code like
  foo = 1;
  atomic_write_barrier ();
  release_flag = 1;
and release_flag could also be a spinlock unlock, for example.

So we want to prevent store/store and load/store reordering, so that the
release_flag assigment is the "last" thing.

Previously, the write barriers prevented -- AFAIU SPARC assembly --
store/load reordering, which is what you'd need a full barrier for on
TSO (e.g., consider Dekker synchronization).  The other kinds of
reordering barriers (e.g., load/store) are implicit on TSO (as on x86).
Thus, the change doesn't fix a correctness issue (at least if using
TSO!) but just a performance issue.

Could someone who cares about SPARC please review and test this?
commit 5adee7234e1ca9ea7b8998a096c369cddeea47c8
Author: Torvald Riegel <triegel@redhat.com>
Date:   Wed Oct 29 19:14:14 2014 +0100

    Fix SPARC atomic_write_barrier.

diff --git a/sysdeps/sparc/sparc32/bits/atomic.h b/sysdeps/sparc/sparc32/bits/atomic.h
index 1b4175d..2ae2eaa 100644
--- a/sysdeps/sparc/sparc32/bits/atomic.h
+++ b/sysdeps/sparc/sparc32/bits/atomic.h
@@ -346,8 +346,8 @@ extern uint64_t _dl_hwcap __attribute__((weak));
 #define atomic_write_barrier()						\
   do {									\
      if (__atomic_is_v9)						\
-       /* membar  #StoreLoad | #StoreStore */				\
-       __asm __volatile (".word 0x8143e00a" : : : "memory");		\
+       /* membar  #LoadStore | #StoreStore */				\
+       __asm __volatile (".word 0x8143e00c" : : : "memory");		\
      else								\
        __asm __volatile ("" : : : "memory");				\
   } while (0)
diff --git a/sysdeps/sparc/sparc32/sparcv9/bits/atomic.h b/sysdeps/sparc/sparc32/sparcv9/bits/atomic.h
index 8441de3..7644796 100644
--- a/sysdeps/sparc/sparc32/sparcv9/bits/atomic.h
+++ b/sysdeps/sparc/sparc32/sparcv9/bits/atomic.h
@@ -99,4 +99,4 @@ typedef uintmax_t uatomic_max_t;
 #define atomic_read_barrier() \
   __asm __volatile ("membar #LoadLoad | #LoadStore" : : : "memory")
 #define atomic_write_barrier() \
-  __asm __volatile ("membar #StoreLoad | #StoreStore" : : : "memory")
+  __asm __volatile ("membar #LoadStore | #StoreStore" : : : "memory")
diff --git a/sysdeps/sparc/sparc64/bits/atomic.h b/sysdeps/sparc/sparc64/bits/atomic.h
index ccb7319..2bca42b 100644
--- a/sysdeps/sparc/sparc64/bits/atomic.h
+++ b/sysdeps/sparc/sparc64/bits/atomic.h
@@ -120,4 +120,4 @@ typedef uintmax_t uatomic_max_t;
 #define atomic_read_barrier() \
   __asm __volatile ("membar #LoadLoad | #LoadStore" : : : "memory")
 #define atomic_write_barrier() \
-  __asm __volatile ("membar #StoreLoad | #StoreStore" : : : "memory")
+  __asm __volatile ("membar #LoadStore | #StoreStore" : : : "memory")

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]