This is the mail archive of the libc-alpha@sourceware.org mailing list for the glibc project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [PATCH] Fix underflow reporting and tie up loose ends in sparcsoft-fp.


From: David Miller <davem@davemloft.net>
Date: Tue, 29 May 2012 16:01:15 -0400 (EDT)

> From: Richard Henderson <rth@twiddle.net>
> Date: Tue, 29 May 2012 10:44:31 -0700
> 
>> The thing that the former code does that the later does not is
>> raise SIGFPE in the event that the exception is not masked.
> 
> The CPU will take the FPU exception when you write the bits into the
> FSR if any bits found in CEXC are also set in TEM.
> 
> I've tested this.

Out of curiosity I tested some more cases than I did previously
and this trick doesn't work in all cases.

I'll thus have to do things differently.

One option is to mimick what sparc64 does and not use the exception
simulator.  Instead, sparc64's soft-fp code actually executes the real
long double instruction and lets the kernel simulate the exception
generation and thus generate the SIGFPE.

Another option is to put back the exception simulation code and simply
get rid of the code that tries to generate underflow or overflow all
by itself.  Just always execute the float operation that will generate
both underflow/overflow and inexact.

If underflow/overflow is enabled in the trap enable mask, the cpu will
do the right thing and only report underflow/overflow and not inexact.
If it is not enabled in the trap enable mask, we want to set both bits.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]