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[PATCH 2/2] Rewrite fraiseexcpt for Renesas sh4
- From: Nobuhiro Iwamatsu <iwamatsu at nigauri dot org>
- To: libc-alpha at sourceware dot org
- Cc: Nobuhiro Iwamatsu <iwamatsu at nigauri dot org>
- Date: Tue, 24 May 2011 14:26:06 +0900
- Subject: [PATCH 2/2] Rewrite fraiseexcpt for Renesas sh4
- References: <1306214766-25971-1-git-send-email-iwamatsu@nigauri.org>
2011-05-24 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* sysdeps/sh/sh4/fpu/fraiseexcpt.c:
Rewrite fraiseexcpt for Renesas sh4. The exception does not occur
only by having validated the bit of the fpu exception.
It is necessary for us to produce an exception using FPU order
intentionally.
---
ChangeLog | 8 +++++++
sysdeps/sh/sh4/fpu/fraiseexcpt.c | 42 ++++++++++++++++++++++++++++++++-----
2 files changed, 44 insertions(+), 6 deletions(-)
diff --git a/ChangeLog b/ChangeLog
index d2bbe9c..0323b52 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,11 @@
+2011-05-24 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+ * sysdeps/sh/sh4/fpu/fraiseexcpt.c:
+ Rewrite fraiseexcpt for Renesas sh4. The exception does not occur
+ only by having validated the bit of the fpu exception.
+ It is necessary for us to produce an exception using FPU order
+ intentionally.
+
2011-05-23 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* sysdeps/sh/sh4/fpu/fedisblxcpt.c:
diff --git a/sysdeps/sh/sh4/fpu/fraiseexcpt.c b/sysdeps/sh/sh4/fpu/fraiseexcpt.c
index f67ec15..a6b73c7 100644
--- a/sysdeps/sh/sh4/fpu/fraiseexcpt.c
+++ b/sysdeps/sh/sh4/fpu/fraiseexcpt.c
@@ -1,6 +1,7 @@
/* Raise given exceptions.
- Copyright (C) 1997, 1998, 2000, 2002 Free Software Foundation, Inc.
+ Copyright (C) 1997, 1998, 2000, 2002, 2011 Free Software Foundation, Inc.
This file is part of the GNU C Library.
+ Contributed by Nobuhiro Iwamatsu <iwamatsu@nigauri.org>, 2011
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
@@ -25,11 +26,40 @@ int
feraiseexcept (int excepts)
{
/* Raise exceptions represented by EXPECTS. */
- fexcept_t temp;
- _FPU_GETCW (temp);
- temp |= (excepts & FE_ALL_EXCEPT);
- temp |= (excepts & FE_ALL_EXCEPT) << 5;
- _FPU_SETCW (temp);
+ /* inexact */
+ if (excepts & FE_INEXACT)
+ {
+ double d = 1.0, x = 3.0;
+ __asm__ __volatile__ ("fdiv %1, %0" : "+d" (d) : "d" (x));
+ }
+
+ /* underflow. */
+ if (excepts & FE_UNDERFLOW)
+ {
+ long double d = LDBL_MIN, x = 10;
+ __asm__ __volatile__ ("fdiv %1, %0" : "+d" (d) : "d" (x));
+ }
+
+ /* overflow */
+ if (excepts & FE_OVERFLOW)
+ {
+ long double d = LDBL_MAX;
+ __asm__ __volatile__ ("fmul %0, %0" : "+d" (d) : "d" (d));
+ }
+
+ /* division by zero */
+ if (excepts & FE_DIVBYZERO)
+ {
+ double d = 1.0, x = 0.0;
+ __asm__ __volatile__ ("fdiv %1, %0" : "+d" (d) : "d" (x));
+ }
+
+ /* invalid */
+ if (excepts & FE_INVALID)
+ {
+ double d = HUGE_VAL, x = 0.0;
+ __asm__ __volatile__ ("fmul %1, %0" : "+d" (d) : "d" (x));
+ }
return 0;
}
--
1.7.5.1