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Re: PATCH: Fix ll/sc for mips (take 3)
- From: Ralf Baechle <ralf at oss dot sgi dot com>
- To: Hartvig Ekner <hartvige at mips dot com>
- Cc: "Maciej W. Rozycki" <macro at ds2 dot pg dot gda dot pl>, Justin Carlson <justinca at ri dot cmu dot edu>, Daniel Jacobowitz <dan at debian dot org>, "H . J . Lu" <hjl at lucon dot org>, Dominic Sweetman <dom at algor dot co dot uk>, GNU C Library <libc-alpha at sources dot redhat dot com>, linux-mips at oss dot sgi dot com
- Date: Tue, 5 Feb 2002 19:59:12 +0100
- Subject: Re: PATCH: Fix ll/sc for mips (take 3)
- References: <Pine.GSO.3.96.1020205131750.9674Efirstname.lastname@example.org> <200202051238.NAA03846@copsun18.mips.com>
On Tue, Feb 05, 2002 at 01:38:34PM +0100, Hartvig Ekner wrote:
> Some of MIPS's cores do externalize the event of a "LL" and make it
> visible on the bus interface. Similarly, the SC is externalized and
> requires a go/nogo response from the system logic. Think of it as
> putting a shared LLAddr & LLBit outside the processor. The SC will
> only succeed if the internal LLBit is ok *and* the external logic gives
> the go-ahead as well.
> The reasoning behind all this is that one can then utilize LL/SC in
> multi CPU systems without full coherency support being required.
> But then again, this might not be relevant for MIPS/Linux as it will not
> run without full HW coherency on multiple CPUs?
Linux could easily be hacked into handle such a configuration as a cluster.
Anything else would be a pretty large job.