GNU C Library master sources branch release/2.26/master updated. glibc-2.26-190-gdc40423

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http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=dc40423dba7208ded2ec293c9a2938269f944ee8

commit dc40423dba7208ded2ec293c9a2938269f944ee8
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Fri Nov 2 11:14:05 2018 +0100

    x86: Fix Haswell CPU string flags (BZ#23709)
    
    Th commit 'Disable TSX on some Haswell processors.' (2702856bf4) changed the
    default flags for Haswell models.  Previously, new models were handled by the
    default switch path, which assumed a Core i3/i5/i7 if AVX is available. After
    the patch, Haswell models (0x3f, 0x3c, 0x45, 0x46) do not set the flags
    Fast_Rep_String, Fast_Unaligned_Load, Fast_Unaligned_Copy, and
    Prefer_PMINUB_for_stringop (only the TSX one).
    
    This patch fixes it by disentangle the TSX flag handling from the memory
    optimization ones.  The strstr case cited on patch now selects the
    __strstr_sse2_unaligned as expected for the Haswell cpu.
    
    Checked on x86_64-linux-gnu.
    
    	[BZ #23709]
    	* sysdeps/x86/cpu-features.c (init_cpu_features): Set TSX bits
    	independently of other flags.
    
    (cherry picked from commit c3d8dc45c9df199b8334599a6cbd98c9950dba62)

diff --git a/ChangeLog b/ChangeLog
index c6dfc5e..17a9232 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2018-10-23  Adhemerval Zanella  <adhemerval.zanella@linaro.org>
+
+	[BZ #23709]
+	* sysdeps/x86/cpu-features.c (init_cpu_features): Set TSX bits
+	independently of other flags.
+
 2017-12-18  Joseph Myers  <joseph@codesourcery.com>
 
 	* nptl/tst-attr3.c: Include <libc-diag.h>.
diff --git a/NEWS b/NEWS
index f6c9a14..d99732f 100644
--- a/NEWS
+++ b/NEWS
@@ -156,6 +156,7 @@ The following bugs are resolved with this release:
   [23459] COMMON_CPUID_INDEX_80000001 isn't populated for Intel processors
   [23562] signal: Use correct type for si_band in siginfo_t
   [23579] libc: Errors misreported in preadv2
+  [23709] Fix CPU string flags for Haswell-type CPUs
 
 Version 2.26
 
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index a66d468..b3a5f4b 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -297,7 +297,13 @@ init_cpu_features (struct cpu_features *cpu_features)
 		    | bit_arch_Fast_Unaligned_Copy
 		    | bit_arch_Prefer_PMINUB_for_stringop);
 	      break;
+	    }
 
+	 /* Disable TSX on some Haswell processors to avoid TSX on kernels that
+	    weren't updated with the latest microcode package (which disables
+	    broken feature by default).  */
+	 switch (model)
+	    {
 	    case 0x3f:
 	      /* Xeon E7 v3 with stepping >= 4 has working TSX.  */
 	      if (stepping >= 4)

-----------------------------------------------------------------------

Summary of changes:
 ChangeLog                  |    6 ++++++
 NEWS                       |    1 +
 sysdeps/x86/cpu-features.c |    6 ++++++
 3 files changed, 13 insertions(+), 0 deletions(-)


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