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GNU C Library master sources branch master updated. glibc-2.28.9000-211-g18ad0de
- From: azanella at sourceware dot org
- To: glibc-cvs at sourceware dot org
- Date: 23 Oct 2018 18:28:17 -0000
- Subject: GNU C Library master sources branch master updated. glibc-2.28.9000-211-g18ad0de
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http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=18ad0de6513bf8a8e4ba757c069e6806d07920f8
commit 18ad0de6513bf8a8e4ba757c069e6806d07920f8
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date: Tue Oct 23 14:53:12 2018 -0300
Fix tst-preadvwritev2 build failure on HURD
Commit 7a16bdbb9ff41 uses IOV_MAX, which is not defined on hurd.
Checked on a build for i686-gnu.
* misc/tst-preadvwritev2-common.c (IOV_MAX): Define if not
defined.
diff --git a/ChangeLog b/ChangeLog
index c5fe2a8..6cb7d60 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,8 @@
2018-10-23 Adhemerval Zanella <adhemerval.zanella@linaro.org>
+ * misc/tst-preadvwritev2-common.c (IOV_MAX): Define if not
+ defined.
+
[BZ #23709]
* sysdeps/x86/cpu-features.c (init_cpu_features): Set TSX bits
independently of other flags.
diff --git a/misc/tst-preadvwritev2-common.c b/misc/tst-preadvwritev2-common.c
index 50b9da3..3098b4a 100644
--- a/misc/tst-preadvwritev2-common.c
+++ b/misc/tst-preadvwritev2-common.c
@@ -37,6 +37,11 @@
#define RWF_SUPPORTED (RWF_HIPRI | RWF_DSYNC | RWF_SYNC | RWF_NOWAIT \
| RWF_APPEND)
+/* Generic uio_lim.h does not define IOV_MAX. */
+#ifndef IOV_MAX
+# define IOV_MAX 1024
+#endif
+
static void
do_test_with_invalid_fd (void)
{
http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=c3d8dc45c9df199b8334599a6cbd98c9950dba62
commit c3d8dc45c9df199b8334599a6cbd98c9950dba62
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date: Thu Oct 11 15:18:40 2018 -0300
x86: Fix Haswell strong flags (BZ#23709)
Th commit 'Disable TSX on some Haswell processors.' (2702856bf4) changed the
default flags for Haswell models. Previously, new models were handled by the
default switch path, which assumed a Core i3/i5/i7 if AVX is available. After
the patch, Haswell models (0x3f, 0x3c, 0x45, 0x46) do not set the flags
Fast_Rep_String, Fast_Unaligned_Load, Fast_Unaligned_Copy, and
Prefer_PMINUB_for_stringop (only the TSX one).
This patch fixes it by disentangle the TSX flag handling from the memory
optimization ones. The strstr case cited on patch now selects the
__strstr_sse2_unaligned as expected for the Haswell cpu.
Checked on x86_64-linux-gnu.
[BZ #23709]
* sysdeps/x86/cpu-features.c (init_cpu_features): Set TSX bits
independently of other flags.
diff --git a/ChangeLog b/ChangeLog
index c0fbf75..c5fe2a8 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2018-10-23 Adhemerval Zanella <adhemerval.zanella@linaro.org>
+
+ [BZ #23709]
+ * sysdeps/x86/cpu-features.c (init_cpu_features): Set TSX bits
+ independently of other flags.
+
2018-10-23 Florian Weimer <fweimer@redhat.com>
* time/tst-mktime2.c (N_STRINGS): Remove.
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index f4e0f5a..80b3054 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -316,7 +316,13 @@ init_cpu_features (struct cpu_features *cpu_features)
| bit_arch_Fast_Unaligned_Copy
| bit_arch_Prefer_PMINUB_for_stringop);
break;
+ }
+ /* Disable TSX on some Haswell processors to avoid TSX on kernels that
+ weren't updated with the latest microcode package (which disables
+ broken feature by default). */
+ switch (model)
+ {
case 0x3f:
/* Xeon E7 v3 with stepping >= 4 has working TSX. */
if (stepping >= 4)
-----------------------------------------------------------------------
Summary of changes:
ChangeLog | 9 +++++++++
misc/tst-preadvwritev2-common.c | 5 +++++
sysdeps/x86/cpu-features.c | 6 ++++++
3 files changed, 20 insertions(+), 0 deletions(-)
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