[Bug libc/18185] Wrong processor count for L2 cache sharing on Silvermont and Knights Landing

["cvs-commit at gcc dot gnu.org" <sourceware-bugzilla at sourceware dot org>]

https://sourceware.org/bugzilla/show_bug.cgi?id=18185

--- Comment #2 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot gnu.org> ---
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "GNU C Library master sources".

The branch, master has been updated
       via  a3d9ab5070b56b49aa91be2887fa5b118012b2cd (commit)
      from  83569fb894050db7430047da2219ca50c68f882a (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=a3d9ab5070b56b49aa91be2887fa5b118012b2cd

commit a3d9ab5070b56b49aa91be2887fa5b118012b2cd
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Tue Mar 31 13:17:51 2015 -0700

    Limit threads sharing L2 cache to 2 for SLM/KNL

    Silvermont and Knights Landing have a modular system design with two cores
    sharing an L2 cache.  If more than 2 cores are detected to shared L2 cache,
    it should be adjusted for Silvermont and Knights Landing.

        [BZ #18185]
        * sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Limit threads
        sharing L2 cache to 2 for Silvermont/Knights Landing.

-----------------------------------------------------------------------

Summary of changes:
 ChangeLog                  |    6 ++++++
 NEWS                       |    2 +-
 sysdeps/x86_64/cacheinfo.c |   23 +++++++++++++++++++++++
 3 files changed, 30 insertions(+), 1 deletions(-)

-- 
You are receiving this mail because:
You are on the CC list for the bug.