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[Bug libc/17403] atomic_full_barrier is incorrect for x86 and x86_64
- From: "triegel at redhat dot com" <sourceware-bugzilla at sourceware dot org>
- To: glibc-bugs at sourceware dot org
- Date: Wed, 17 Sep 2014 19:44:36 +0000
- Subject: [Bug libc/17403] atomic_full_barrier is incorrect for x86 and x86_64
- Auto-submitted: auto-generated
- References: <bug-17403-131 at http dot sourceware dot org/bugzilla/>
https://sourceware.org/bugzilla/show_bug.cgi?id=17403
--- Comment #2 from Torvald Riegel <triegel at redhat dot com> ---
I'm not quite sure about the really old ones such as i486, but the HW memory
model is TSO, which still needs Store/Load barriers -- it's not sequential
consistency that the HW provides. So for stuff like Dekker synchronization you
need mfence. See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
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