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[binutils-gdb] RISC-V: Add RV32E support.
- From: sergiodj+buildbot at sergiodj dot net
- To: gdb-testers at sourceware dot org
- Date: Fri, 18 May 2018 22:02:57 -0400
- Subject: [binutils-gdb] RISC-V: Add RV32E support.
*** TEST RESULTS FOR COMMIT 7f99954970001cfc1b155d877ac2966d77e2c647 ***
Author: Jim Wilson <jimw@sifive.com>
Branch: master
Commit: 7f99954970001cfc1b155d877ac2966d77e2c647
RISC-V: Add RV32E support.
Kito Cheng <kito.cheng@gmail.com>
Monk Chiang <sh.chiang04@gmail.com>
bfd/
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Handle
EF_RISCV_RVE.
binutils/
* readelf.c (get_machine_flags): Handle EF_RISCV_RVE.
gas/
* config/tc-riscv.c (rve_abi): New.
(riscv_set_options): Add rve field. Initialize it.
(riscv_set_rve) New function.
(riscv_set_arch): Support 'e' ISA subset.
(reg_lookup_internal): If rve, check register is available.
(riscv_set_abi): New parameter rve.
(md_parse_option): Pass new argument to riscv_set_abi.
(riscv_after_parse_args): Call riscv_set_rve. If rve_abi, set
EF_RISCV_RVE.
* doc/c-riscv.texi (-mabi): Document new ilp32e argument.
include/
* elf/riscv.h (EF_RISCV_RVE): New define.