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Re: [RFC] gdb/riscv: Add target description support

On Thu, 08 Nov 2018 10:32:57 PST (-0800), wrote:
On 11/8/18 8:07 AM, Andrew Burgess wrote:
This commit adds target description support for riscv.

I've used the split feature approach for specifying the architectural
features, and the CSR feature is auto-generated from the riscv-opc.h
header file.

In general this looks fine to me (as far as I am familiar with the
target descriptions).  The only possible question/comment I have is if
you considered describing fields of specific registers such as the FP
status registers or MSTATUS, etc. as fields in the XML to replace the
current special cases in riscv_print_one_register_info().  I think the
XML can't handle enum values as riscv_print_one_register_info() uses for
some cases, but I think it would be able to handle many of the special
cases in that function.

Some related-ish questions (though not about this patch): I wonder if we
can do things with pseudo registers to automatically derive FFLAGS and
FRM if a target provides FCSR.

One more note: AFAIU, 1.10 of the privilege spec removed hypervisor mode
with the intention of implementing virtualization support differently.
We might want to remove the references to hypervisor mode from riscv-tdep.c
as a result?

The only reference I see is in the PRV decoding, which I think is OK: while the spec doesn't mention hypervisor mode any more, the bit pattern is still there and an upcoming spec will add it back in. I believe the official name is now "hypervisor-extended supervisor mode" but since that's a bit of a mouthfull I still call it hypervisor mode :)

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