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Re: [PATCH] RISC-V: enable have_nonsteppable_watchpoint by default
> > I think MIPS is one. The documentation is not entirely clear but
> > that's what I remember from using it.
> x86 is another. But my question is -- do we know of any RISC-V
> implementation that triggers after the write, given that the spec
> says it should trigger before the write.
That was what I meant as well; I agree with Pedro that we don't
really need to do anything fancy if:
- the spec's recommendation is to trigger before the write
- and we don't know of any system that decided to go against
the recommendation.
The day we discover a system that does in fact go against the
recommendation, we can simply deal with it then and decide what
the best course of action is.
--
Joel