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Re: [PATCH 2/4] Fall back to a default value of 0 for the MISA register.
On Fri, Sep 21, 2018 at 2:27 AM Andrew Burgess
<andrew.burgess@embecosm.com> wrote:
> Jim: Given that we agree that targets should definitely provide a
> value for misa, at a minimum just returning the constant 0. But,
> given that GDB already defaults to 0 in some cases anyway. And the
> spec is quite clear that 0 is the right default value in the absence
> of anything better, would you be OK with a patch that does return a
> default of 0?
The patch to decode an instruction to decide whether to use a
compressed breakpoint or not solves my main problem. There is also
the issue of finding FP register size, but since we only support
rv64gc at the moment, it isn't a serious problem. Also, I think the
linker kernel may already be passing FP info via auxvec/hwcap, so I
think we already have an alternate solution for that which just needs
to be implemented. I haven't looked at that yet. So yes, I think it
is OK to start defaulting misa to 0.
FYI I have a qemu patch, which I may someday finish, that adds XML
register support to the RISC-V qemu system-mode port, which allows
qemu to provide a correct value of misa. We know that misa accesses
already work with embedded targets via OpenOCD. So it is just linux
and freebsd that need to worry about misa.
The qemu patch is here, though it looks like github is confused by
rebasing and the patch isn't readable anymore.
https://github.com/riscv/riscv-qemu/pull/160
I'll have to figure out how to fix that.
Jim