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[PATCH] aarch64 sim big-endian support
- From: Jim Wilson <jim dot wilson at linaro dot org>
- To: gdb-patches at sourceware dot org
- Date: Thu, 2 Jun 2016 19:36:30 -0700
- Subject: [PATCH] aarch64 sim big-endian support
- Authentication-results: sourceware.org; auth=none
On aarch64, code is always little-endian, even when compiling
big-endian, so we need to force little-endian when reading
instructions.
Running the gcc C language testsuite, I get for an aarch64-elf target
# of expected passes 35433
# of unexpected failures 254
# of unsupported tests 131
and for an aarch64_be-elf target with the attached patch I get
# of expected passes 35200
# of unexpected failures 487
# of unsupported tests 131
so this simple patch gets us most of the way there. I haven't tried
looking at the other problems yet.
I also have a dejagnu patch I wrote to make this work, which I will be
submitting to the dejagnu team shortly.
Jim
2016-06-02 Jim Wilson <jim.wilson@linaro.org>
sim/aarch64/
* simulator.c (aarch64_step): New var saved_target_byte_order. Force
byte order to BFD_ENDIAN_LITTLE before pc read, then restore saved
value.
diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index 88cb03d..5a1814c 100644
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -14078,12 +14078,18 @@ static bfd_boolean
aarch64_step (sim_cpu *cpu)
{
uint64_t pc = aarch64_get_PC (cpu);
+ enum bfd_endian saved_target_byte_order;
if (pc == TOP_LEVEL_RETURN_PC)
return FALSE;
aarch64_set_next_PC (cpu, pc + 4);
+
+ /* Code is always little-endian. */
+ saved_target_byte_order = current_target_byte_order;
+ current_target_byte_order = BFD_ENDIAN_LITTLE;
aarch64_get_instr (cpu) = aarch64_get_mem_u32 (cpu, pc);
+ current_target_byte_order = saved_target_byte_order;
TRACE_INSN (cpu, " pc = %" PRIx64 " instr = %08x", pc,
aarch64_get_instr (cpu));