Re: [PATCH] [gdbserver] Disable conditional breakpoints on no-hardware-single-step targets

["Maciej W. Rozycki" <macro at linux-mips dot org>]

On Wed, 6 May 2015, Pedro Alves wrote:

> > It is worse if the arm/thumb interworking is considered.  Nowadays,
> > GDBserver arm backend unconditionally inserts arm breakpoint,
> > 
> >   /* Define an ARM-mode breakpoint; we only set breakpoints in the C
> >      library, which is most likely to be ARM.  If the kernel supports
> >      clone events, we will never insert a breakpoint, so even a Thumb
> >      C library will work; so will mixing EABI/non-EABI gdbserver and
> >      application.  */
> > #ifndef __ARM_EABI__
> >   (const unsigned char *) &arm_breakpoint,
> > #else
> >   (const unsigned char *) &arm_eabi_breakpoint,
> > #endif
> > 
> > note that the comments are no longer valid as C library can be compiled
> > in thumb mode.
> > 
> > When GDBserver steps over a breakpoint in arm mode function, which
> > returns to thumb mode, GDBserver will insert arm mode breakpoint by
> > mistake and the program will crash.  GDBserver alone is unable to
> > determine the arm/thumb mode given a PC address.  See how GDB does
> > it in arm-tdep.c:arm_pc_is_thumb.
> 
> Of a random PC address no, but in gdbserver's case, I think that it
> would work, because we need it to step over a breakpoint that is
> at the current PC.  So we could:
> 
>  #1 - Get the mode of the current PC from the thread's $cpsr register.
> 
>  #2 - Get the mode of the next PC by looking at the instruction that is
>       about to be executed (at current PC).  If bx and blx, which change
>       modes, check the thumb bit of the destination address.
>       For all other instructions, same mode as the current PC.

 A similar issue exists for the three MIPS ISA modes and gdbserver will 
not have enough data to determine which of the two of the MIPS16 and 
microMIPS instruction sets to use for the compressed mode.  Only GDB knows 
that, at the last resort having been told by the user.

  Maciej